example.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_TCO_RESULT" "clk q q~reg0 6.511 ns register " "Info: tco from clock clk to destination pin q through register q~reg0 is 6.511 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.792 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N8; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.163 ns) + CELL(0.542 ns) 2.792 ns q~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(1.163 ns) + CELL(0.542 ns) = 2.792 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "1.705 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 58.35 % " "Info: Total cell delay = 1.629 ns ( 58.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.163 ns 41.65 % " "Info: Total interconnect delay = 1.163 ns ( 41.65 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "2.792 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.563 ns + Longest register pin " "Info: + Longest register to pin delay is 3.563 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC_X33_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "" { q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.159 ns) + CELL(2.404 ns) 3.563 ns q 2 PIN PIN_P9 0 " "Info: 2: + IC(1.159 ns) + CELL(2.404 ns) = 3.563 ns; Loc. = PIN_P9; Fanout = 0; PIN Node = 'q'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "3.563 ns" { q~reg0 q } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns 67.47 % " "Info: Total cell delay = 2.404 ns ( 67.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.159 ns 32.53 % " "Info: Total interconnect delay = 1.159 ns ( 32.53 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "3.563 ns" { q~reg0 q } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "2.792 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "3.563 ns" { q~reg0 q } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "q~reg0 a clk -2.081 ns register " "Info: th for register q~reg0 (data pin = a, clock pin = clk) is -2.081 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.792 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N8; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.163 ns) + CELL(0.542 ns) 2.792 ns q~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(1.163 ns) + CELL(0.542 ns) = 2.792 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "1.705 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 58.35 % " "Info: Total cell delay = 1.629 ns ( 58.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.163 ns 41.65 % " "Info: Total interconnect delay = 1.163 ns ( 41.65 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "2.792 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.973 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns a 1 PIN PIN_M8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_M8; Fanout = 1; PIN Node = 'a'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "" { a } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.663 ns) + CELL(0.223 ns) 4.973 ns q~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(3.663 ns) + CELL(0.223 ns) = 4.973 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "3.886 ns" { a q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.310 ns 26.34 % " "Info: Total cell delay = 1.310 ns ( 26.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.663 ns 73.66 % " "Info: Total interconnect delay = 3.663 ns ( 73.66 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "4.973 ns" { a q~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "2.792 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "4.973 ns" { a q~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk q q~reg0 6.511 ns register " "Info: Minimum tco from clock clk to destination pin q through register q~reg0 is 6.511 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.792 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N8; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.163 ns) + CELL(0.542 ns) 2.792 ns q~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(1.163 ns) + CELL(0.542 ns) = 2.792 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "1.705 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 58.35 % " "Info: Total cell delay = 1.629 ns ( 58.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.163 ns 41.65 % " "Info: Total interconnect delay = 1.163 ns ( 41.65 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "2.792 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.563 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.563 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC_X33_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "" { q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.159 ns) + CELL(2.404 ns) 3.563 ns q 2 PIN PIN_P9 0 " "Info: 2: + IC(1.159 ns) + CELL(2.404 ns) = 3.563 ns; Loc. = PIN_P9; Fanout = 0; PIN Node = 'q'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "3.563 ns" { q~reg0 q } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns 67.47 % " "Info: Total cell delay = 2.404 ns ( 67.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.159 ns 32.53 % " "Info: Total interconnect delay = 1.159 ns ( 32.53 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "3.563 ns" { q~reg0 q } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "2.792 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "3.563 ns" { q~reg0 q } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 12 16:02:56 2007 " "Info: Processing ended: Sat May 12 16:02:56 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}