example.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 12 16:02:55 2007 " "Info: Processing started: Sat May 12 16:02:55 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off example -c example --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off example -c example --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 3 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register paths exist for clock clk" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "q~reg0 b clk 2.325 ns register " "Info: tsu for register q~reg0 (data pin = b, clock pin = clk) is 2.325 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.107 ns + Longest pin register " "Info: + Longest pin to register delay is 5.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns b 1 PIN PIN_T9 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_T9; Fanout = 1; PIN Node = 'b'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "" { b } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.701 ns) + CELL(0.319 ns) 5.107 ns q~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(3.701 ns) + CELL(0.319 ns) = 5.107 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "4.020 ns" { b q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.406 ns 27.53 % " "Info: Total cell delay = 1.406 ns ( 27.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.701 ns 72.47 % " "Info: Total interconnect delay = 3.701 ns ( 72.47 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "5.107 ns" { b q~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.792 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk 1 CLK PIN_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N8; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.163 ns) + CELL(0.542 ns) 2.792 ns q~reg0 2 REG LC_X33_Y1_N2 1 " "Info: 2: + IC(1.163 ns) + CELL(0.542 ns) = 2.792 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'q~reg0'" {  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "1.705 ns" { clk q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" "" "" { Text "D:/VHDL数字逻辑教程/2.2D触发器+与非门/example.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns 58.35 % " "Info: Total cell delay = 1.629 ns ( 58.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.163 ns 41.65 % " "Info: Total interconnect delay = 1.163 ns ( 41.65 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "2.792 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "5.107 ns" { b q~reg0 } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example_cmp.qrpt" Compiler "example" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/2.2D触发器+与非门/db/example.quartus_db" { Floorplan "" "" "2.792 ns" { clk q~reg0 } "NODE_NAME" } } }  } 0}