example.fit.summary

来自「一些很好的FPGA设计实例」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Sat May 12 16:02:19 2007
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : example
Top-level Entity Name : example
Family : Stratix
Total logic elements : 1 / 10,570 ( < 1 % )
Total pins : 4 / 336 ( 1 % )
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )
Device : EP1S10F484C5
Timing Models : Production