fuyongqi.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 56 行

----------方案１：using a signal(not ok)---------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------
entity fuyongqi is
  port( a,b,c,d,s0,s1: in std_logic;
        y: out std_logic);
end fuyongqi;
-------------------------------------------------------
architecture not_ok of fuyongqi is
 signal sel: integer range 0 to3;
begin
 process(a,b,c,d,s0,s1)
 begin
    sel <= 0;
    if (s0 = '1' )then sel <= sel+1;
    end if;
    if (s1 = '1')then sel <= sel+2;
    end if;
    case sel is
     when 0 => y <= a;
     when 1 => y <= b;
     when 2 => y <= c;
     when 3 => y <= d;
    end case;
  end process;
end not_ok;
--------------------------------------------------------

---------------方案２：using a variable(ok)-------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------
entity fuyongqi is
  port( a,b,c,d,s0,s1: in std_logic;
        y: out std_logic);
end fuyongqi;
-------------------------------------------------------
architecture ok of fuyongqi is
begin
 process(a,b,c,d,s0,s1)
variable sel: integer range 0 to3;
 begin
    sel =: 0;
    if (s0 = '1' )then sel := sel+1;
    end if;
    if (s1 = '1')then sel := sel+2;
    end if;
    case sel is
     when 0 => y <= a;
     when 1 => y <= b;
     when 2 => y <= c;
     when 3 => y <= d;
    end case;
  end process;
end not_ok;