add.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 28 行

----------方案1：in/out=signed-----------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-----------------------------------------
entity add is
  port (a,b clk: in signed (3 downto 0);
      sum: out signed (4 downto 0));
end add;
-----------------------------------------
architecture add1 of add is
begin 
sum <= a+b;
end add1;
-----------方案2:out=integer-------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-----------------------------------
entity add2 is
  port (a,b clk: in signed (3 downto 0);
      sum: out integer range -16 to 15 );
end add2;
------------------------------------
architecture add3 of add2 is
begin 
sum <= conv_integer (a+b);
end add3;