suocunqi.map.qmsg

一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 16 10:48:53 2007 " "Info: Processing started: Wed May 16 10:48:53 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off suocunqi -c suocunqi " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off suocunqi -c suocunqi" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "suocunqi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file suocunqi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 suocunqi-suocunqi " "Info: Found design unit 1: suocunqi-suocunqi" {  } { { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" "suocunqi-suocunqi" "" { Text "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" 34 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 suocunqi " "Info: Found entity 1: suocunqi" {  } { { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" "suocunqi" "" { Text "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" 29 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "1 " "Info: Ignored 1 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "1 " "Info: Ignored 1 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "4 " "Info: Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "1 " "Info: Implemented 1 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 16 10:48:56 2007 " "Info: Processing ended: Wed May 16 10:48:56 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}