suocunqi.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 16 10:49:12 2007 " "Info: Processing started: Wed May 16 10:49:12 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off suocunqi -c suocunqi " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off suocunqi -c suocunqi" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "d q 6.700 ns Longest " "Info: Longest tpd from source pin d to destination pin q is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns d 1 PIN PIN_184 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_184; Fanout = 1; PIN Node = 'd'" {  } { { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" Compiler "suocunqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi.quartus_db" { Floorplan "" "" "" { d } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 2.400 ns q\$latch~27 2 COMB LC8_E6 2 " "Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 2.400 ns; Loc. = LC8_E6; Fanout = 2; COMB Node = 'q\$latch~27'" {  } { { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" Compiler "suocunqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi.quartus_db" { Floorplan "" "" "1.100 ns" { d q$latch~27 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(3.800 ns) 6.700 ns q 3 PIN PIN_119 0 " "Info: 3: + IC(0.500 ns) + CELL(3.800 ns) = 6.700 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'q'" {  } { { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" Compiler "suocunqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi.quartus_db" { Floorplan "" "" "4.300 ns" { q$latch~27 q } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.100 ns 91.04 % " "Info: Total cell delay = 6.100 ns ( 91.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 8.96 % " "Info: Total interconnect delay = 0.600 ns ( 8.96 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" Compiler "suocunqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi.quartus_db" { Floorplan "" "" "6.700 ns" { d q$latch~27 q } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk q 6.500 ns Shortest " "Info: Shortest tpd from source pin clk to destination pin q is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 PIN PIN_182 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_182; Fanout = 1; PIN Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" Compiler "suocunqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 2.200 ns q\$latch~27 2 COMB LC8_E6 2 " "Info: 2: + IC(0.100 ns) + CELL(0.800 ns) = 2.200 ns; Loc. = LC8_E6; Fanout = 2; COMB Node = 'q\$latch~27'" {  } { { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" Compiler "suocunqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi.quartus_db" { Floorplan "" "" "0.900 ns" { clk q$latch~27 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(3.800 ns) 6.500 ns q 3 PIN PIN_119 0 " "Info: 3: + IC(0.500 ns) + CELL(3.800 ns) = 6.500 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'q'" {  } { { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" Compiler "suocunqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi.quartus_db" { Floorplan "" "" "4.300 ns" { q$latch~27 q } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/suocunqi.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.900 ns 90.77 % " "Info: Total cell delay = 5.900 ns ( 90.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 9.23 % " "Info: Total interconnect delay = 0.600 ns ( 9.23 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi_cmp.qrpt" Compiler "suocunqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.7用guarded block实现锁存器/db/suocunqi.quartus_db" { Floorplan "" "" "6.500 ns" { clk q$latch~27 q } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 16 10:49:14 2007 " "Info: Processing ended: Wed May 16 10:49:14 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}