suocunqi.vhd

一些很好的FPGA设计实例

--块语句：simple block 和　guarded block
 ---------------------------------------------------
------architecture example...
------begin
------...
------block1: block
------begin
------...
------end block block1;
------...
------block2: block
------begin
------...
------end block biock2;
------end example;
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--只有当表达式的值为真时，在guarded block 中前面有关键词guarded的语句才能执行
---语法结构：
--label: block(表达式)
--[声明部分]
--begin
--[语句]
--end block label
-----------------但在其内部可以构造时序电路，但不常见
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------
entity suocunqi is
   port (d,clk : in std_logic;
         q: out std_logic);
end suocunqi;
--------------------------
architecture suocunqi of suocunqi is
begin 
b1: block (clk ='1')
begin
  q <= guarded d;----卫式语句
   end block b1;
end suocunqi;
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