generateyuju.map.rpt

来自「一些很好的FPGA设计实例」· RPT 代码 · 共 160 行

Analysis & Synthesis report for generateyuju
Wed May 16 10:26:42 2007
Version 4.1 Build 181 06/29/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Wed May 16 10:26:42 2007        ;
; Quartus II Version          ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name               ; generateyuju                             ;
; Top-level Entity Name       ; generateyuju                             ;
; Family                      ; Stratix                                  ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Disk space/compilation speed tradeoff                              ; Normal       ; Normal        ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; Family name                                                        ; Stratix      ; Stratix       ;
; Top-level entity name                                              ; generateyuju ; generateyuju  ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; DSP Block Balancing                                                ; Auto         ; Auto          ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;
; Ignore SOFT Buffers                                                ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off          ; Off           ;
; Optimization Technique -- Stratix/Stratix GX                       ; Balanced     ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70           ; 70            ;
; Auto Carry Chains                                                  ; On           ; On            ;
; Auto Open-Drain Pins                                               ; On           ; On            ;
; Remove Duplicate Logic                                             ; On           ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off          ; Off           ;
; Perform gate-level register retiming                               ; Off          ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On           ; On            ;
; Auto ROM Replacement                                               ; On           ; On            ;
; Auto RAM Replacement                                               ; On           ; On            ;
; Auto DSP Block Replacement                                         ; On           ; On            ;
; Auto Shift Register Replacement                                    ; On           ; On            ;
; Auto Clock Enable Replacement                                      ; On           ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On           ; On            ;
; Auto RAM Block Balancing                                           ; On           ; On            ;
; Auto Resource Sharing                                              ; Off          ; Off           ;
; Allow Any RAM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any ROM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any Shift Register Size For Recognition                      ; Off          ; Off           ;
+--------------------------------------------------------------------+--------------+---------------+


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+------------------+---------------------+
; File Name        ; Used in Netlist     ;
+------------------+---------------------+
; generateyuju.vhd ; yes                 ;
+------------------+---------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed May 16 10:26:39 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off generateyuju -c generateyuju
Info: Found 2 design units, including 1 entities, in source file generateyuju.vhd
    Info: Found design unit 1: generateyuju-yiweiqi
    Info: Found entity 1: generateyuju
Warning: Tied undriven net row[4][7] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[4][6] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[4][5] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[4][4] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[4][3] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[4][2] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[4][1] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[4][0] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[3][7] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[3][6] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[3][5] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[3][4] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[3][3] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[3][2] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[3][1] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[3][0] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[2][7] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[2][6] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[2][5] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[2][4] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[2][3] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[2][2] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[2][1] at generateyuju.vhd(56) to GND or VCC
Warning: Tied undriven net row[2][0] at generateyuju.vhd(56) to GND or VCC
Error: Verilog HDL or VHDL error: Net inp[0] is already driven by input port inp[3]
Error: Port inp[3] is declared at generateyuju.vhd(48)
Error: Verilog HDL or VHDL error: Net inp[0] is already driven by input port inp[2]
Error: Port inp[2] is declared at generateyuju.vhd(48)
Error: Verilog HDL or VHDL error: Net inp[0] is already driven by input port inp[1]
Error: Port inp[1] is declared at generateyuju.vhd(48)
Error: Verilog HDL or VHDL error: Net inp[0] is already driven by input port inp[0]
Error: Port inp[0] is declared at generateyuju.vhd(48)
Error: Can't elaborate user hierarchy 
Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 24 warnings
    Error: Processing ended: Wed May 16 10:26:41 2007
    Error: Elapsed time: 00:00:02