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📄 simple_fsm.tan.qmsg

📁 一些很好的FPGA设计实例
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register pr_state x~reg0 422.12 MHz Internal " "Info: Clock clk Internal fmax is restricted to 422.12 MHz between source register pr_state and destination register x~reg0" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.619 ns + Longest register register " "Info: + Longest register to register delay is 0.619 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pr_state 1 REG LC_X52_Y30_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y30_N2; Fanout = 2; REG Node = 'pr_state'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { pr_state } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.223 ns) 0.619 ns x~reg0 2 REG LC_X52_Y30_N4 1 " "Info: 2: + IC(0.396 ns) + CELL(0.223 ns) = 0.619 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "0.619 ns" { pr_state x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.223 ns 36.03 % " "Info: Total cell delay = 0.223 ns ( 36.03 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.396 ns 63.97 % " "Info: Total interconnect delay = 0.396 ns ( 63.97 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "0.619 ns" { pr_state x~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.772 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.505 ns) + CELL(0.542 ns) 2.772 ns x~reg0 2 REG LC_X52_Y30_N4 1 " "Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.047 ns" { clk x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.71 % " "Info: Total cell delay = 1.267 ns ( 45.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.505 ns 54.29 % " "Info: Total interconnect delay = 1.505 ns ( 54.29 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk x~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.772 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.505 ns) + CELL(0.542 ns) 2.772 ns pr_state 2 REG LC_X52_Y30_N2 2 " "Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N2; Fanout = 2; REG Node = 'pr_state'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.047 ns" { clk pr_state } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.71 % " "Info: Total cell delay = 1.267 ns ( 45.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.505 ns 54.29 % " "Info: Total interconnect delay = 1.505 ns ( 54.29 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk pr_state } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk pr_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "0.619 ns" { pr_state x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk pr_state } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "pr_state d clk 2.734 ns register " "Info: tsu for register pr_state (data pin = d, clock pin = clk) is 2.734 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.496 ns + Longest pin register " "Info: + Longest pin to register delay is 5.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns d 1 PIN PIN_B3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_B3; Fanout = 1; PIN Node = 'd'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { d } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.704 ns) + CELL(0.705 ns) 5.496 ns pr_state 2 REG LC_X52_Y30_N2 2 " "Info: 2: + IC(3.704 ns) + CELL(0.705 ns) = 5.496 ns; Loc. = LC_X52_Y30_N2; Fanout = 2; REG Node = 'pr_state'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "4.409 ns" { d pr_state } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.792 ns 32.61 % " "Info: Total cell delay = 1.792 ns ( 32.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.704 ns 67.39 % " "Info: Total interconnect delay = 3.704 ns ( 67.39 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "5.496 ns" { d pr_state } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.772 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.505 ns) + CELL(0.542 ns) 2.772 ns pr_state 2 REG LC_X52_Y30_N2 2 " "Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N2; Fanout = 2; REG Node = 'pr_state'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.047 ns" { clk pr_state } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.71 % " "Info: Total cell delay = 1.267 ns ( 45.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.505 ns 54.29 % " "Info: Total interconnect delay = 1.505 ns ( 54.29 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk pr_state } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "5.496 ns" { d pr_state } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk pr_state } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk x x~reg0 6.098 ns register " "Info: tco from clock clk to destination pin x through register x~reg0 is 6.098 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.772 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.505 ns) + CELL(0.542 ns) 2.772 ns x~reg0 2 REG LC_X52_Y30_N4 1 " "Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.047 ns" { clk x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.71 % " "Info: Total cell delay = 1.267 ns ( 45.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.505 ns 54.29 % " "Info: Total interconnect delay = 1.505 ns ( 54.29 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk x~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.170 ns + Longest register pin " "Info: + Longest register to pin delay is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x~reg0 1 REG LC_X52_Y30_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.794 ns) + CELL(2.376 ns) 3.170 ns x 2 PIN PIN_D2 0 " "Info: 2: + IC(0.794 ns) + CELL(2.376 ns) = 3.170 ns; Loc. = PIN_D2; Fanout = 0; PIN Node = 'x'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "3.170 ns" { x~reg0 x } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns 74.95 % " "Info: Total cell delay = 2.376 ns ( 74.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.794 ns 25.05 % " "Info: Total interconnect delay = 0.794 ns ( 25.05 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "3.170 ns" { x~reg0 x } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "3.170 ns" { x~reg0 x } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "x~reg0 a clk -2.228 ns register " "Info: th for register x~reg0 (data pin = a, clock pin = clk) is -2.228 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.772 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.505 ns) + CELL(0.542 ns) 2.772 ns x~reg0 2 REG LC_X52_Y30_N4 1 " "Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.047 ns" { clk x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 45.71 % " "Info: Total cell delay = 1.267 ns ( 45.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.505 ns 54.29 % " "Info: Total interconnect delay = 1.505 ns ( 54.29 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk x~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns a 1 PIN PIN_G7 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_G7; Fanout = 1; PIN Node = 'a'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "" { a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.694 ns) + CELL(0.319 ns) 5.100 ns x~reg0 2 REG LC_X52_Y30_N4 1 " "Info: 2: + IC(3.694 ns) + CELL(0.319 ns) = 5.100 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "4.013 ns" { a x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.406 ns 27.57 % " "Info: Total cell delay = 1.406 ns ( 27.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.694 ns 72.43 % " "Info: Total interconnect delay = 3.694 ns ( 72.43 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "5.100 ns" { a x~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "2.772 ns" { clk x~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm_cmp.qrpt" Compiler "simple_fsm" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/db/simple_fsm.quartus_db" { Floorplan "" "" "5.100 ns" { a x~reg0 } "NODE_NAME" } } }  } 0}
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