simple_fsm.tan.qmsg

来自「一些很好的FPGA设计实例」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 17 11:55:43 2007 " "Info: Processing started: Thu May 17 11:55:43 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off simple_fsm -c simple_fsm --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off simple_fsm -c simple_fsm --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" "" "" { Text "d:/vhdl数字逻辑教程/8.3 简单的fsm#2/simple_fsm.vhd" 5 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}