simple_fsm.tan.rpt

一些很好的FPGA设计实例

+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From   ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A   ; None         ; 6.098 ns   ; x~reg0 ; x  ; clk        ;
+-------+--------------+------------+--------+----+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -2.228 ns ; a    ; x~reg0   ; clk      ;
; N/A           ; None        ; -2.354 ns ; b    ; x~reg0   ; clk      ;
; N/A           ; None        ; -2.615 ns ; rst  ; x~reg0   ; clk      ;
; N/A           ; None        ; -2.624 ns ; d    ; pr_state ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+------------------------------------------------------------------------------+
; Minimum tco                                                                  ;
+---------------+------------------+----------------+--------+----+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From   ; To ; From Clock ;
+---------------+------------------+----------------+--------+----+------------+
; N/A           ; None             ; 6.098 ns       ; x~reg0 ; x  ; clk        ;
+---------------+------------------+----------------+--------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu May 17 11:55:43 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off simple_fsm -c simple_fsm --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 422.12 MHz between source register pr_state and destination register x~reg0
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.619 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y30_N2; Fanout = 2; REG Node = 'pr_state'
            Info: 2: + IC(0.396 ns) + CELL(0.223 ns) = 0.619 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'
            Info: Total cell delay = 0.223 ns ( 36.03 % )
            Info: Total interconnect delay = 0.396 ns ( 63.97 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 2.772 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'
                Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'
                Info: Total cell delay = 1.267 ns ( 45.71 % )
                Info: Total interconnect delay = 1.505 ns ( 54.29 % )
            Info: - Longest clock path from clock clk to source register is 2.772 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'
                Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N2; Fanout = 2; REG Node = 'pr_state'
                Info: Total cell delay = 1.267 ns ( 45.71 % )
                Info: Total interconnect delay = 1.505 ns ( 54.29 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register pr_state (data pin = d, clock pin = clk) is 2.734 ns
    Info: + Longest pin to register delay is 5.496 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_B3; Fanout = 1; PIN Node = 'd'
        Info: 2: + IC(3.704 ns) + CELL(0.705 ns) = 5.496 ns; Loc. = LC_X52_Y30_N2; Fanout = 2; REG Node = 'pr_state'
        Info: Total cell delay = 1.792 ns ( 32.61 % )
        Info: Total interconnect delay = 3.704 ns ( 67.39 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock clk to destination register is 2.772 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N2; Fanout = 2; REG Node = 'pr_state'
        Info: Total cell delay = 1.267 ns ( 45.71 % )
        Info: Total interconnect delay = 1.505 ns ( 54.29 % )
Info: tco from clock clk to destination pin x through register x~reg0 is 6.098 ns
    Info: + Longest clock path from clock clk to source register is 2.772 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'
        Info: Total cell delay = 1.267 ns ( 45.71 % )
        Info: Total interconnect delay = 1.505 ns ( 54.29 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.170 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'
        Info: 2: + IC(0.794 ns) + CELL(2.376 ns) = 3.170 ns; Loc. = PIN_D2; Fanout = 0; PIN Node = 'x'
        Info: Total cell delay = 2.376 ns ( 74.95 % )
        Info: Total interconnect delay = 0.794 ns ( 25.05 % )
Info: th for register x~reg0 (data pin = a, clock pin = clk) is -2.228 ns
    Info: + Longest clock path from clock clk to destination register is 2.772 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'
        Info: Total cell delay = 1.267 ns ( 45.71 % )
        Info: Total interconnect delay = 1.505 ns ( 54.29 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_G7; Fanout = 1; PIN Node = 'a'
        Info: 2: + IC(3.694 ns) + CELL(0.319 ns) = 5.100 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'
        Info: Total cell delay = 1.406 ns ( 27.57 % )
        Info: Total interconnect delay = 3.694 ns ( 72.43 % )
Info: Minimum tco from clock clk to destination pin x through register x~reg0 is 6.098 ns
    Info: + Shortest clock path from clock clk to source register is 2.772 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.505 ns) + CELL(0.542 ns) = 2.772 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'
        Info: Total cell delay = 1.267 ns ( 45.71 % )
        Info: Total interconnect delay = 1.505 ns ( 54.29 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Shortest register to pin delay is 3.170 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y30_N4; Fanout = 1; REG Node = 'x~reg0'
        Info: 2: + IC(0.794 ns) + CELL(2.376 ns) = 3.170 ns; Loc. = PIN_D2; Fanout = 0; PIN Node = 'x'
        Info: Total cell delay = 2.376 ns ( 74.95 % )
        Info: Total interconnect delay = 0.794 ns ( 25.05 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu May 17 11:55:44 2007
    Info: Elapsed time: 00:00:01