simple_fsm.fit.eqn

一些很好的FPGA设计实例

--A1L8Q is x~reg0 at LC_X52_Y30_N4
--operation mode is normal

A1L8Q_lut_out = b & (a # pr_state) # !b & a & !pr_state;
A1L8Q = DFFEA(A1L8Q_lut_out, GLOBAL(clk), VCC, , !rst, , );


--pr_state is pr_state at LC_X52_Y30_N2
--operation mode is normal

pr_state_lut_out = !pr_state;
pr_state = DFFEA(pr_state_lut_out, GLOBAL(clk), !rst, , d, , );


--b is b at PIN_D3
--operation mode is input

b = INPUT();


--a is a at PIN_G7
--operation mode is input

a = INPUT();


--clk is clk at PIN_L2
--operation mode is input

clk = INPUT();


--rst is rst at PIN_B2
--operation mode is input

rst = INPUT();


--d is d at PIN_B3
--operation mode is input

d = INPUT();


--x is x at PIN_D2
--operation mode is output

x = OUTPUT(A1L8Q);