cufaqi.tan.qmsg

来自「一些很好的FPGA设计实例」· QMSG 代码 · 共 13 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 16 11:23:16 2007 " "Info: Processing started: Wed May 16 11:23:16 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off cufaqi -c cufaqi " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off cufaqi -c cufaqi" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "d:/vhdl数字逻辑教程/6.1带有异步复位端的d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/6.1带有异步复位端的d触发器/cufaqi.vhd" 12 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register paths exist for clock clk" {  } {  } 0}