jishuqi.tan.rpt

一些很好的FPGA设计实例

; tco                                                                     ;
+-------+--------------+------------+-------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To       ; From Clock ;
+-------+--------------+------------+-------------+----------+------------+
; N/A   ; None         ; 7.969 ns   ; pr_state~24 ; count[0] ; clk        ;
; N/A   ; None         ; 7.675 ns   ; pr_state~26 ; count[0] ; clk        ;
; N/A   ; None         ; 7.432 ns   ; pr_state~27 ; count[2] ; clk        ;
; N/A   ; None         ; 7.330 ns   ; pr_state~25 ; count[2] ; clk        ;
; N/A   ; None         ; 7.296 ns   ; pr_state~28 ; count[0] ; clk        ;
; N/A   ; None         ; 7.296 ns   ; pr_state~22 ; count[1] ; clk        ;
; N/A   ; None         ; 7.191 ns   ; pr_state~27 ; count[1] ; clk        ;
; N/A   ; None         ; 7.189 ns   ; pr_state~20 ; count[0] ; clk        ;
; N/A   ; None         ; 7.128 ns   ; pr_state~23 ; count[1] ; clk        ;
; N/A   ; None         ; 7.006 ns   ; pr_state~26 ; count[2] ; clk        ;
; N/A   ; None         ; 6.753 ns   ; pr_state~26 ; count[1] ; clk        ;
; N/A   ; None         ; 6.753 ns   ; pr_state~24 ; count[2] ; clk        ;
; N/A   ; None         ; 6.744 ns   ; pr_state~22 ; count[0] ; clk        ;
; N/A   ; None         ; 6.602 ns   ; pr_state~29 ; count[3] ; clk        ;
; N/A   ; None         ; 6.349 ns   ; pr_state~28 ; count[3] ; clk        ;
+-------+--------------+------------+-------------+----------+------------+


+-----------------------------------------------------------------------------------------+
; Minimum tco                                                                             ;
+---------------+------------------+----------------+-------------+----------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From        ; To       ; From Clock ;
+---------------+------------------+----------------+-------------+----------+------------+
; N/A           ; None             ; 6.349 ns       ; pr_state~28 ; count[3] ; clk        ;
; N/A           ; None             ; 6.602 ns       ; pr_state~29 ; count[3] ; clk        ;
; N/A           ; None             ; 6.744 ns       ; pr_state~22 ; count[0] ; clk        ;
; N/A           ; None             ; 6.753 ns       ; pr_state~24 ; count[2] ; clk        ;
; N/A           ; None             ; 6.753 ns       ; pr_state~26 ; count[1] ; clk        ;
; N/A           ; None             ; 7.006 ns       ; pr_state~26 ; count[2] ; clk        ;
; N/A           ; None             ; 7.128 ns       ; pr_state~23 ; count[1] ; clk        ;
; N/A           ; None             ; 7.189 ns       ; pr_state~20 ; count[0] ; clk        ;
; N/A           ; None             ; 7.191 ns       ; pr_state~27 ; count[1] ; clk        ;
; N/A           ; None             ; 7.296 ns       ; pr_state~22 ; count[1] ; clk        ;
; N/A           ; None             ; 7.296 ns       ; pr_state~28 ; count[0] ; clk        ;
; N/A           ; None             ; 7.330 ns       ; pr_state~25 ; count[2] ; clk        ;
; N/A           ; None             ; 7.432 ns       ; pr_state~27 ; count[2] ; clk        ;
; N/A           ; None             ; 7.675 ns       ; pr_state~26 ; count[0] ; clk        ;
; N/A           ; None             ; 7.969 ns       ; pr_state~24 ; count[0] ; clk        ;
+---------------+------------------+----------------+-------------+----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu May 17 10:50:55 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off jishuqi -c jishuqi --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 422.12 MHz between source register pr_state~29 and destination register pr_state~20
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.632 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N9; Fanout = 2; REG Node = 'pr_state~29'
            Info: 2: + IC(0.409 ns) + CELL(0.223 ns) = 0.632 ns; Loc. = LC_X1_Y30_N6; Fanout = 2; REG Node = 'pr_state~20'
            Info: Total cell delay = 0.223 ns ( 35.28 % )
            Info: Total interconnect delay = 0.409 ns ( 64.72 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 2.835 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'
                Info: 2: + IC(1.568 ns) + CELL(0.542 ns) = 2.835 ns; Loc. = LC_X1_Y30_N6; Fanout = 2; REG Node = 'pr_state~20'
                Info: Total cell delay = 1.267 ns ( 44.69 % )
                Info: Total interconnect delay = 1.568 ns ( 55.31 % )
            Info: - Longest clock path from clock clk to source register is 2.835 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'
                Info: 2: + IC(1.568 ns) + CELL(0.542 ns) = 2.835 ns; Loc. = LC_X1_Y30_N9; Fanout = 2; REG Node = 'pr_state~29'
                Info: Total cell delay = 1.267 ns ( 44.69 % )
                Info: Total interconnect delay = 1.568 ns ( 55.31 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock clk to destination pin count[0] through register pr_state~24 is 7.969 ns
    Info: + Longest clock path from clock clk to source register is 2.835 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(1.568 ns) + CELL(0.542 ns) = 2.835 ns; Loc. = LC_X1_Y30_N0; Fanout = 3; REG Node = 'pr_state~24'
        Info: Total cell delay = 1.267 ns ( 44.69 % )
        Info: Total interconnect delay = 1.568 ns ( 55.31 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.978 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N0; Fanout = 3; REG Node = 'pr_state~24'
        Info: 2: + IC(0.532 ns) + CELL(0.366 ns) = 0.898 ns; Loc. = LC_X2_Y30_N2; Fanout = 1; COMB Node = 'reduce_or~51'
        Info: 3: + IC(0.482 ns) + CELL(0.075 ns) = 1.455 ns; Loc. = LC_X1_Y30_N7; Fanout = 1; COMB Node = 'reduce_or~2'
        Info: 4: + IC(1.119 ns) + CELL(2.404 ns) = 4.978 ns; Loc. = PIN_B20; Fanout = 0; PIN Node = 'count[0]'
        Info: Total cell delay = 2.845 ns ( 57.15 % )
        Info: Total interconnect delay = 2.133 ns ( 42.85 % )
Info: Minimum tco from clock clk to destination pin count[3] through register pr_state~28 is 6.349 ns
    Info: + Shortest clock path from clock clk to source register is 2.835 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(1.568 ns) + CELL(0.542 ns) = 2.835 ns; Loc. = LC_X1_Y30_N4; Fanout = 3; REG Node = 'pr_state~28'
        Info: Total cell delay = 1.267 ns ( 44.69 % )
        Info: Total interconnect delay = 1.568 ns ( 55.31 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Shortest register to pin delay is 3.358 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N4; Fanout = 3; REG Node = 'pr_state~28'
        Info: 2: + IC(0.000 ns) + CELL(0.230 ns) = 0.230 ns; Loc. = LC_X1_Y30_N4; Fanout = 1; COMB Node = 'count~0'
        Info: 3: + IC(0.752 ns) + CELL(2.376 ns) = 3.358 ns; Loc. = PIN_E19; Fanout = 0; PIN Node = 'count[3]'
        Info: Total cell delay = 2.606 ns ( 77.61 % )
        Info: Total interconnect delay = 0.752 ns ( 22.39 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu May 17 10:50:56 2007
    Info: Elapsed time: 00:00:01