jishuqi.vhd

一些很好的FPGA设计实例

--摩尔型状态机，仅取决于内部寄存器的当前状态------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity jishuqi is
   port( rst , clk : in std_logic;
         count: out std_logic_vector(3 downto 0));
end jishuqi ;
-------------------------------
architecture jishuqi  of jishuqi  is
   type state is (zero,one,two,three,four,five,six,seven,eight,nine);
   signal pr_state, nx_state : state;
begin
--------------------lower section------------------
process (rst,clk)
begin
  if(rst = '1')then
     pr_state <= zero;
  elsif (clk 'event and clk = '1')then
  pr_state <= nx_state;
  end if;
end process;
-----------------------upper section----------------
process ( pr_state)
begin
  case pr_state is
 when zero =>
       count <= "0000";
       nx_state <= one;
 when one =>
       count <= "0001";
       nx_state <= two;
 when two =>
       count <= "0010";
       nx_state <= three;
 when three =>
       count <= "0011";
       nx_state <= four;
 when four =>
       count <= "0100";
       nx_state <= five;
 when five =>
       count <= "0101";
       nx_state <= six;
 when six =>
       count <= "0110";
       nx_state <= seven;
 when seven =>
       count <= "0111";
       nx_state <= eight;
 when eight =>
       count <= "1000";
       nx_state <= nine;
 when nine =>
       count <= "1001";
       nx_state <= zero;
  end case;
end process;
end jishuqi ;
-----------------代码综合得到的寄存器的数量等于对fsm所有状态进行编码所需的位数
-----------------如果使用二进制的编码方式，则需要寄存器的数量是[log2n],其中n是总的状态数