jishuqi.fit.eqn

一些很好的FPGA设计实例

--A1L71Q is pr_state~29 at LC_X1_Y30_N9
--operation mode is normal

A1L71Q_lut_out = A1L61Q;
A1L71Q = DFFEA(A1L71Q_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , );


--A1L7 is count~0 at LC_X1_Y30_N4
--operation mode is normal

A1L61Q_qfbk = A1L61Q;
A1L7 = A1L61Q_qfbk # A1L71Q;

--A1L61Q is pr_state~28 at LC_X1_Y30_N4
--operation mode is normal

A1L61Q_sload_eqn = A1L51Q;
A1L61Q = DFFEA(A1L61Q_sload_eqn, GLOBAL(clk), !GLOBAL(rst), , , , );


--A1L31Q is pr_state~25 at LC_X1_Y30_N2
--operation mode is normal

A1L31Q_lut_out = A1L21Q;
A1L31Q = DFFEA(A1L31Q_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , );


--A1L51Q is pr_state~27 at LC_X1_Y30_N5
--operation mode is normal

A1L51Q_lut_out = A1L41Q;
A1L51Q = DFFEA(A1L51Q_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , );


--A1L91 is reduce_or~49 at LC_X1_Y30_N0
--operation mode is normal

A1L21Q_qfbk = A1L21Q;
A1L91 = A1L51Q # A1L31Q # A1L21Q_qfbk # A1L41Q;

--A1L21Q is pr_state~24 at LC_X1_Y30_N0
--operation mode is normal

A1L21Q_sload_eqn = A1L11Q;
A1L21Q = DFFEA(A1L21Q_sload_eqn, GLOBAL(clk), !GLOBAL(rst), , , , );


--A1L11Q is pr_state~23 at LC_X1_Y30_N1
--operation mode is normal

A1L11Q_sload_eqn = A1L01Q;
A1L11Q = DFFEA(A1L11Q_sload_eqn, GLOBAL(clk), !GLOBAL(rst), , , , );


--A1L02 is reduce_or~50 at LC_X1_Y30_N8
--operation mode is normal

A1L41Q_qfbk = A1L41Q;
A1L02 = A1L01Q # A1L51Q # A1L41Q_qfbk # A1L11Q;

--A1L41Q is pr_state~26 at LC_X1_Y30_N8
--operation mode is normal

A1L41Q_sload_eqn = A1L31Q;
A1L41Q = DFFEA(A1L41Q_sload_eqn, GLOBAL(clk), !GLOBAL(rst), , , , );


--A1L12 is reduce_or~51 at LC_X2_Y30_N2
--operation mode is normal

A1L12 = !A1L21Q & !A1L41Q;


--A1L8Q is pr_state~20 at LC_X1_Y30_N6
--operation mode is normal

A1L8Q_lut_out = !A1L71Q;
A1L8Q = DFFEA(A1L8Q_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , );


--A1L81 is reduce_or~2 at LC_X1_Y30_N7
--operation mode is normal

A1L01Q_qfbk = A1L01Q;
A1L81 = A1L61Q # A1L01Q_qfbk # !A1L12 # !A1L8Q;

--A1L01Q is pr_state~22 at LC_X1_Y30_N7
--operation mode is normal

A1L01Q_sload_eqn = A1L9Q;
A1L01Q = DFFEA(A1L01Q_sload_eqn, GLOBAL(clk), !GLOBAL(rst), , , , );


--A1L9Q is pr_state~21 at LC_X1_Y30_N3
--operation mode is normal

A1L9Q_lut_out = !A1L8Q;
A1L9Q = DFFEA(A1L9Q_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , );


--clk is clk at PIN_L2
--operation mode is input

clk = INPUT();


--rst is rst at PIN_L3
--operation mode is input

rst = INPUT();


--count[3] is count[3] at PIN_E19
--operation mode is output

count[3] = OUTPUT(A1L7);


--count[2] is count[2] at PIN_D20
--operation mode is output

count[2] = OUTPUT(A1L91);


--count[1] is count[1] at PIN_C20
--operation mode is output

count[1] = OUTPUT(A1L02);


--count[0] is count[0] at PIN_B20
--operation mode is output

count[0] = OUTPUT(!A1L81);