jishuqi.tan.summary

一些很好的FPGA设计实例

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.969 ns
From           : pr_state~24
To             : count[0]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.349 ns
From           : pr_state~28
To             : count[3]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 422.12 MHz ( period = 2.369 ns )
From           : pr_state~25
To             : pr_state~26
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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