jishuqi.map.rpt

一些很好的FPGA设计实例

; pr_state.six   ; 0           ; 0           ; 0           ; 1           ; 0           ; 0           ; 0           ; 0           ; 0           ; 1           ;
; pr_state.seven ; 0           ; 0           ; 1           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 1           ;
; pr_state.eight ; 0           ; 1           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 1           ;
; pr_state.nine  ; 1           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ; 1           ;
+----------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |jishuqi                   ; 15 (15)     ; 10           ; 0           ; 0            ; 0       ; 0         ; 0         ; 6    ; 0            ; 5 (5)        ; 10 (10)           ; 0 (0)            ; 0 (0)           ; |jishuqi            ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in d:/vhdl数字逻辑教程/8.1bcd计数器/jishuqi.map.eqn.


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-------------+--------------------------+
; File Name   ; Used in Netlist          ;
+-------------+--------------------------+
; jishuqi.vhd ; yes                      ;
+-------------+--------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Logic cells                     ; 15        ;
; Total combinational functions   ; 5         ;
; Total 4-input functions         ; 3         ;
; Total 3-input functions         ; 0         ;
; Total 2-input functions         ; 2         ;
; Total 1-input functions         ; 0         ;
; Total 0-input functions         ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 10        ;
; I/O pins                        ; 6         ;
; Maximum fan-out node            ; clk       ;
; Maximum fan-out                 ; 10        ;
; Total fan-out                   ; 50        ;
; Average fan-out                 ; 2.38      ;
+---------------------------------+-----------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 15    ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 5     ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 10    ;
; Number of cells with combinational logic only          ; 5     ;
; Number of cells with registers only                    ; 10    ;
; Number of cells with combinational logic and registers ; 0     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 10    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu May 17 10:48:44 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off jishuqi -c jishuqi
Info: Found 2 design units, including 1 entities, in source file jishuqi.vhd
    Info: Found design unit 1: jishuqi-jishuqi
    Info: Found entity 1: jishuqi
Info: State machine |jishuqi|pr_state contains 10 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |jishuqi|pr_state
Info: Encoding result for state machine |jishuqi|pr_state
    Info: Completed encoding using 10 state bits
        Info: Encoded state bit pr_state~29
        Info: Encoded state bit pr_state~28
        Info: Encoded state bit pr_state~27
        Info: Encoded state bit pr_state~26
        Info: Encoded state bit pr_state~25
        Info: Encoded state bit pr_state~24
        Info: Encoded state bit pr_state~23
        Info: Encoded state bit pr_state~22
        Info: Encoded state bit pr_state~21
        Info: Encoded state bit pr_state~20
    Info: State |jishuqi|pr_state.zero uses code string 0000000000
    Info: State |jishuqi|pr_state.one uses code string 0000000011
    Info: State |jishuqi|pr_state.two uses code string 0000000101
    Info: State |jishuqi|pr_state.three uses code string 0000001001
    Info: State |jishuqi|pr_state.four uses code string 0000010001
    Info: State |jishuqi|pr_state.five uses code string 0000100001
    Info: State |jishuqi|pr_state.six uses code string 0001000001
    Info: State |jishuqi|pr_state.seven uses code string 0010000001
    Info: State |jishuqi|pr_state.eight uses code string 0100000001
    Info: State |jishuqi|pr_state.nine uses code string 1000000001
Info: Implemented 21 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 4 output pins
    Info: Implemented 15 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu May 17 10:48:49 2007
    Info: Elapsed time: 00:00:04