jishuqi.map.eqn

一些很好的FPGA设计实例

--A1L9 is add~77
--operation mode is normal

A1L9 = din[1] $ din[0] $ din[2] $ din[3];


--A1L6 is add~62
--operation mode is normal

A1L6 = A1L9 $ din[5] $ din[4] $ din[6];


--A1L21 is add~622
--operation mode is normal

A1L21 = din[6] & (A1L9 # din[5] $ din[4]) # !din[6] & A1L9 & (din[5] $ din[4]);


--A1L01 is add~82
--operation mode is normal

A1L01 = din[3] & (din[2] & (!din[1] # !din[0]) # !din[2] & (din[0] # din[1])) # !din[3] & (din[2] & (din[0] # din[1]) # !din[2] & din[0] & din[1]);


--A1L7 is add~67
--operation mode is normal

A1L7 = A1L21 $ A1L01 $ (din[5] & din[4]);


--A1L1 is add~26
--operation mode is normal

A1L1 = din[5] & din[4];


--A1L11 is add~84
--operation mode is normal

A1L11 = din[3] & din[2] & din[0] & din[1];


--A1L8 is add~72
--operation mode is normal

A1L8 = A1L11 $ (A1L21 & (A1L1 # A1L01) # !A1L21 & A1L1 & A1L01);


--A1L5 is add~49
--operation mode is normal

A1L5 = A1L6 & din[7] & A1L7 & A1L8;


--A1L4 is add~47
--operation mode is normal

A1L4 = A1L8 $ (A1L6 & din[7] & A1L7);


--A1L3 is add~42
--operation mode is normal

A1L3 = A1L7 $ (A1L6 & din[7]);


--A1L2 is add~37
--operation mode is normal

A1L2 = A1L6 $ din[7];


--din[1] is din[1]
--operation mode is input

din[1] = INPUT();


--din[0] is din[0]
--operation mode is input

din[0] = INPUT();


--din[2] is din[2]
--operation mode is input

din[2] = INPUT();


--din[3] is din[3]
--operation mode is input

din[3] = INPUT();


--din[5] is din[5]
--operation mode is input

din[5] = INPUT();


--din[4] is din[4]
--operation mode is input

din[4] = INPUT();


--din[6] is din[6]
--operation mode is input

din[6] = INPUT();


--din[7] is din[7]
--operation mode is input

din[7] = INPUT();


--ones[3] is ones[3]
--operation mode is output

ones[3] = OUTPUT(A1L5);


--ones[2] is ones[2]
--operation mode is output

ones[2] = OUTPUT(A1L4);


--ones[1] is ones[1]
--operation mode is output

ones[1] = OUTPUT(A1L3);


--ones[0] is ones[0]
--operation mode is output

ones[0] = OUTPUT(A1L2);