jishuqi.map.summary

来自「一些很好的FPGA设计实例」· SUMMARY 代码 · 共 10 行

Flow Status : Successful - Wed May 16 14:47:28 2007
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : jishuqi
Top-level Entity Name : jishuqi
Family : ACEX1K
Total logic elements : 12
Total pins : 12
Total memory bits : 0
Total PLLs : 0