vhdl1.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 42 行

---模八计数器，都需使用寄存器来保存３位的当前计数值

entity jishuqi is
   port (clk,rst: in  bit;
         count: out integer range 0 to 7);
end jishuqi;
------------------------------
architecture jishuqi of jishuqi is
begin 
   process(clk,rst)
   variable temp : integer range 0 to 7;
   begin 
   if (rst = '1')then     
   temp := 0;
   elsif (clk 'event and clk = '1')then
     temp := temp+1;
end if;
count <= temp;
end process;
end jishuqi;
--------------------------------



entity jishuqi is
   port (clk,rst: in  bit;
         count: buffer integer range 0 to 7);
end jishuqi;
------------------------------
architecture jishuqi of jishuqi is
begin 
   process(clk,rst)
   begin 
   if (rst = '1')then     
   count <= 0;
   elsif (clk 'event and clk = '1')then
    count <= count+1;
end if;
end process;
end jishuqi;
---------------
--没有用到std_logic,所以没有进行std_logic_1164包集的声明