yiweijcq.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 59 行

----------------方案１-------------------------------------
entity yiweijcq is
   port (din, clk: in bit;
          dout: out bit);
end yiweijcq;
------------------------------------------------------
architecture yiweijcq of yiweijcq is
begin 
process(clk)
    variable a,b,c:bit;
    begin
    if(clk 'event and clk = '1')then
      dout <= c;--由于c的值被赋给dout之前没有对c赋过值，这样的代码经过编译后会生成寄存器
      c:= b;      ---用于存储process上一次执行后各个变量的值
      b:= a;
      a:= din;
    end if;
 end process;
end yiweijcq;
--------------------------------------------------------
------------------方案２---------------------------------
entity yiweijcq is
   port (din, clk: in bit;
          dout: out bit);
end yiweijcq;
------------------------------------------------------
architecture yiweijcq of yiweijcq is
signal a,b,c : bit;--信号依次被赋值，整个电路是在时钟上升沿的触发下工作的，编译后生成４个寄存器
begin 
process(clk)
    begin
    if(clk 'event and clk = '1')then
      a<= din;
      b<= a;
      c<= b;
      dout <= c;
    end if;
 end process;
end yiweijcq;   
--------------------------------------------------------------
-------------------------方案３-------------------------------
entity yiweijcq is
   port (din, clk: in bit;
          dout: out bit);
end yiweijcq;
--------------------------------------------------------------
architecture yiweijcq of yiweijcq is
begin 
process(clk)
    variable a,b,c:bit;
    begin
    if(clk 'event and clk = '1')then
    a:= din;--由于变量的赋值立即生效，所以53-56可以简化为一行，等效于c:=din
    b:= a;
    c:= b;
    dout <= c;--c 的值赋给了信号dout，最终会生成一个寄存器
    end if;
 end process;
end yiweijcq;