jicunqi.map.rpt

一些很好的FPGA设计实例

Analysis & Synthesis report for jicunqi
Wed May 16 17:25:43 2007
Version 4.1 Build 181 06/29/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Wed May 16 17:25:43 2007        ;
; Quartus II Version          ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name               ; jicunqi                                  ;
; Top-level Entity Name       ; jicunqi                                  ;
; Family                      ; ACEX1K                                   ;
+-----------------------------+------------------------------------------+


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                       ;
+------------------------------------------------------+--------------+---------------+
; Option                                               ; Setting      ; Default Value ;
+------------------------------------------------------+--------------+---------------+
; Family name                                          ; ACEX1K       ; Stratix       ;
; Create Debugging Nodes for IP Cores                  ; off          ; off           ;
; Disk space/compilation speed tradeoff                ; Normal       ; Normal        ;
; Preserve fewer node names                            ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation            ; Off          ; Off           ;
; Verilog Version                                      ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                         ; VHDL93       ; VHDL93        ;
; Top-level entity name                                ; jicunqi      ; jicunqi       ;
; State Machine Processing                             ; Auto         ; Auto          ;
; NOT Gate Push-Back                                   ; On           ; On            ;
; Power-Up Don't Care                                  ; On           ; On            ;
; Remove Redundant Logic Cells                         ; Off          ; Off           ;
; Remove Duplicate Registers                           ; On           ; On            ;
; Ignore CARRY Buffers                                 ; Off          ; Off           ;
; Ignore CASCADE Buffers                               ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                            ; Off          ; Off           ;
; Ignore LCELL Buffers                                 ; Off          ; Off           ;
; Ignore SOFT Buffers                                  ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                       ; Off          ; Off           ;
; Auto Implement in ROM                                ; Off          ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area         ; Area          ;
; Carry Chain Length -- FLEX 10K                       ; 32           ; 32            ;
; Cascade Chain Length                                 ; 2            ; 2             ;
; Auto Carry Chains                                    ; On           ; On            ;
; Auto Open-Drain Pins                                 ; On           ; On            ;
; Remove Duplicate Logic                               ; On           ; On            ;
; Auto ROM Replacement                                 ; On           ; On            ;
; Auto RAM Replacement                                 ; On           ; On            ;
; Auto Clock Enable Replacement                        ; On           ; On            ;
; Auto Resource Sharing                                ; Off          ; Off           ;
; Allow Any RAM Size For Recognition                   ; Off          ; Off           ;
; Allow Any ROM Size For Recognition                   ; Off          ; Off           ;
+------------------------------------------------------+--------------+---------------+


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-----------+----------------------------+
; File Name ; Used in Netlist            ;
+-----------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed May 16 17:25:41 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off jicunqi -c jicunqi
Error: VHDL syntax error at jicunqi.vhd(22) near text "<="; expecting ";"
Error: VHDL type mismatch error at jicunqi.vhd(22): type of indexed object that is assigned or mapped to target object must match target object type  void
Error: VHDL syntax error at jicunqi.vhd(23) near text "process"; expecting "if"
Error: VHDL error at jicunqi.vhd(24): type of identifier jicunqi does not agree with its usage as  void type
Info: Found 0 design units, including 0 entities, in source file jicunqi.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings
    Error: Processing ended: Wed May 16 17:25:43 2007
    Error: Elapsed time: 00:00:02