jicunqi.fit.eqn

一些很好的FPGA设计实例

--internal[0] is internal[0] at LC7_A13
--operation mode is normal

internal[0]_lut_out = internal[1];
internal[0] = DFFEA(internal[0]_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , );


--internal[1] is internal[1] at LC1_A13
--operation mode is normal

internal[1]_lut_out = internal[2];
internal[1] = DFFEA(internal[1]_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , );


--internal[2] is internal[2] at LC2_A13
--operation mode is normal

internal[2]_lut_out = internal[3];
internal[2] = DFFEA(internal[2]_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , );


--internal[3] is internal[3] at LC3_A13
--operation mode is normal

internal[3]_lut_out = d;
internal[3] = DFFEA(internal[3]_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , );


--clk is clk at PIN_39
--operation mode is input

clk = INPUT();


--rst is rst at PIN_91
--operation mode is input

rst = INPUT();


--d is d at PIN_89
--operation mode is input

d = INPUT();


--q is q at PIN_9
--operation mode is output

q = OUTPUT(internal[0]);