jicunqi.tan.rpt

一些很好的FPGA设计实例

+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-------------+----+------------+
; Slack ; Required tco ; Actual tco ; From        ; To ; From Clock ;
+-------+--------------+------------+-------------+----+------------+
; N/A   ; None         ; 6.300 ns   ; internal[0] ; q  ; clk        ;
+-------+--------------+------------+-------------+----+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To          ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A           ; None        ; 0.100 ns  ; d    ; internal[3] ; clk      ;
+---------------+-------------+-----------+------+-------------+----------+


+-----------------------------------------------------------------------------------+
; Minimum tco                                                                       ;
+---------------+------------------+----------------+-------------+----+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From        ; To ; From Clock ;
+---------------+------------------+----------------+-------------+----+------------+
; N/A           ; None             ; 6.300 ns       ; internal[0] ; q  ; clk        ;
+---------------+------------------+----------------+-------------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed May 16 17:21:02 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off jicunqi -c jicunqi
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 250.0 MHz between source register internal[3] and destination register internal[2]
    Info: fmax restricted to Clock High delay (2.0 ns) plus Clock Low delay (2.0 ns) : restricted to 4.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A13; Fanout = 1; REG Node = 'internal[3]'
            Info: 2: + IC(0.100 ns) + CELL(0.400 ns) = 0.500 ns; Loc. = LC2_A13; Fanout = 1; REG Node = 'internal[2]'
            Info: Total cell delay = 0.400 ns ( 80.00 % )
            Info: Total interconnect delay = 0.100 ns ( 20.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 1.500 ns
                Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2_A13; Fanout = 1; REG Node = 'internal[2]'
                Info: Total cell delay = 1.300 ns ( 86.67 % )
                Info: Total interconnect delay = 0.200 ns ( 13.33 % )
            Info: - Longest clock path from clock clk to source register is 1.500 ns
                Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC3_A13; Fanout = 1; REG Node = 'internal[3]'
                Info: Total cell delay = 1.300 ns ( 86.67 % )
                Info: Total interconnect delay = 0.200 ns ( 13.33 % )
        Info: + Micro clock to output delay of source is 0.300 ns
        Info: + Micro setup delay of destination is 0.400 ns
Info: tsu for register internal[3] (data pin = d, clock pin = clk) is 1.000 ns
    Info: + Longest pin to register delay is 2.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 1; PIN Node = 'd'
        Info: 2: + IC(0.400 ns) + CELL(0.400 ns) = 2.100 ns; Loc. = LC3_A13; Fanout = 1; REG Node = 'internal[3]'
        Info: Total cell delay = 1.700 ns ( 80.95 % )
        Info: Total interconnect delay = 0.400 ns ( 19.05 % )
    Info: + Micro setup delay of destination is 0.400 ns
    Info: - Shortest clock path from clock clk to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC3_A13; Fanout = 1; REG Node = 'internal[3]'
        Info: Total cell delay = 1.300 ns ( 86.67 % )
        Info: Total interconnect delay = 0.200 ns ( 13.33 % )
Info: tco from clock clk to destination pin q through register internal[0] is 6.300 ns
    Info: + Longest clock path from clock clk to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC7_A13; Fanout = 1; REG Node = 'internal[0]'
        Info: Total cell delay = 1.300 ns ( 86.67 % )
        Info: Total interconnect delay = 0.200 ns ( 13.33 % )
    Info: + Micro clock to output delay of source is 0.300 ns
    Info: + Longest register to pin delay is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A13; Fanout = 1; REG Node = 'internal[0]'
        Info: 2: + IC(0.700 ns) + CELL(3.800 ns) = 4.500 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 3.800 ns ( 84.44 % )
        Info: Total interconnect delay = 0.700 ns ( 15.56 % )
Info: th for register internal[3] (data pin = d, clock pin = clk) is 0.100 ns
    Info: + Longest clock path from clock clk to destination register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC3_A13; Fanout = 1; REG Node = 'internal[3]'
        Info: Total cell delay = 1.300 ns ( 86.67 % )
        Info: Total interconnect delay = 0.200 ns ( 13.33 % )
    Info: + Micro hold delay of destination is 0.700 ns
    Info: - Shortest pin to register delay is 2.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 1; PIN Node = 'd'
        Info: 2: + IC(0.400 ns) + CELL(0.400 ns) = 2.100 ns; Loc. = LC3_A13; Fanout = 1; REG Node = 'internal[3]'
        Info: Total cell delay = 1.700 ns ( 80.95 % )
        Info: Total interconnect delay = 0.400 ns ( 19.05 % )
Info: Minimum tco from clock clk to destination pin q through register internal[0] is 6.300 ns
    Info: + Shortest clock path from clock clk to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC7_A13; Fanout = 1; REG Node = 'internal[0]'
        Info: Total cell delay = 1.300 ns ( 86.67 % )
        Info: Total interconnect delay = 0.200 ns ( 13.33 % )
    Info: + Micro clock to output delay of source is 0.300 ns
    Info: + Shortest register to pin delay is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A13; Fanout = 1; REG Node = 'internal[0]'
        Info: 2: + IC(0.700 ns) + CELL(3.800 ns) = 4.500 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 3.800 ns ( 84.44 % )
        Info: Total interconnect delay = 0.700 ns ( 15.56 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed May 16 17:21:03 2007
    Info: Elapsed time: 00:00:01