jicunqi.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 45 行

----------------方案１-------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------
entity jicunqi is 
     port (d,clk,rst :in std_logic;
          q: out std_logic);
end jicunqi;
------------------------------------------------------
architecture jicunqi of jicunqi is
signal internal: std_logic_vector(3 downto 0);
begin 
process(clk,rst)
    begin
  if (rst ='1')then
   internal <=(others=> '0');
    elsif(clk 'event and clk = '1')then
     internal <= d & internal(3 downto 1);
  end if;
 end process;
q<=internal(0);
end jicunqi;
------------------------------------------------------
???????------------方案２-------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------
entity jicunqi is 
     port (d,clk,rst :in std_logic;
          q: out std_logic);
end jicunqi;
------------------------------------------------------
architecture jicunqi of jicunqi is
begin 
process(clk,rst)
variable  internal: std_logic_vector(3 downto 0);
    begin
  if (rst ='1')then
   internal := (others=> '0');
    elsif(clk 'event and clk = '1')then
     internal := d & internal(3 downto 1);
  end if
 q <= internal(0);
 end process;
end jicunqi;