luojidanyuan.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

---------------------------------
entity luijidanyuan is 
port ( a,b : in std_logic_vector(7 downto 0);
       sel : in std_logic_vector(3 downto 0);
       cin : out std_logic;
       y   : out std_logic_vector(7 downto 0));
end luijidanyuan;
---------------------------------------------
architecture dataflow of luijidanyuan is
  signal arith, logic: std_logic_vector(7 downto 0);
begin
---------------arithmetic unit-----------------
   when sel (2 downto 0 )select
    arith <= a when "000",
           a+1 when "001",
           a-1 when "010",
           b   when "011",
           b+1 when "100",
           b-1 when "101",
           a+b when "110",
           a+b+cin when others;
-----------------logic unit------------------------
  when sel (2 downto 0 )select
    logic <= not a when "000",
             not b when "001",
             a and b when "010",
             a or b when "011",
             a nand b when "100",
             a nor b when "101",
             a xor b when "110",
             not(a xor b) when others;
------------------mux-----------------------------
with sel(3) select
       y<= arith when '0';
           logic when  others;
end dataflow;    
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