cufaqi.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 18 行

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--带有同步复位，上升沿触发的d触发器
library ieee;
use ieee.std_logic_1164.all;
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entity cufaqi is
  port (d, clk, rst: in std_logic;
          q: out std_logic);
end cufaqi;
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architecture cufaqi of cufaqi is
begin 
b1: block (clk 'event and clk = '1')--卫式表达式
begin 
q <= guarded '0' when rst = '1' else d;--卫式语句
end block b1;
end cufaqi;
--只有卫式表达式为真且rst为高电平时，才执行q<='0'