jishuqi.tan.rpt

一些很好的FPGA设计实例

; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; \count:temp[2] ; \count:temp[1] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; \count:temp[3] ; \count:temp[3] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; \count:temp[0] ; \count:temp[2] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; \count:temp[1] ; \count:temp[2] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; \count:temp[1] ; \count:temp[1] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; \count:temp[2] ; \count:temp[2] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; \count:temp[0] ; \count:temp[1] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 250.00 MHz ( period = 4.000 ns ) ; \count:temp[0] ; \count:temp[0] ; clk        ; clk      ; None                        ; None                      ; None                    ;
+-------+------------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+----------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From           ; To       ; From Clock ;
+-------+--------------+------------+----------------+----------+------------+
; N/A   ; None         ; 6.300 ns   ; \count:temp[0] ; digit[0] ; clk        ;
; N/A   ; None         ; 6.300 ns   ; \count:temp[2] ; digit[2] ; clk        ;
; N/A   ; None         ; 6.200 ns   ; \count:temp[1] ; digit[1] ; clk        ;
; N/A   ; None         ; 6.200 ns   ; \count:temp[3] ; digit[3] ; clk        ;
+-------+--------------+------------+----------------+----------+------------+


+--------------------------------------------------------------------------------------------+
; Minimum tco                                                                                ;
+---------------+------------------+----------------+----------------+----------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From           ; To       ; From Clock ;
+---------------+------------------+----------------+----------------+----------+------------+
; N/A           ; None             ; 6.200 ns       ; \count:temp[3] ; digit[3] ; clk        ;
; N/A           ; None             ; 6.200 ns       ; \count:temp[1] ; digit[1] ; clk        ;
; N/A           ; None             ; 6.300 ns       ; \count:temp[2] ; digit[2] ; clk        ;
; N/A           ; None             ; 6.300 ns       ; \count:temp[0] ; digit[0] ; clk        ;
+---------------+------------------+----------------+----------------+----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu May 17 12:26:23 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off jishuqi -c jishuqi
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 250.0 MHz between source register \count:temp[3] and destination register \count:temp[1]
    Info: fmax restricted to Clock High delay (2.0 ns) plus Clock Low delay (2.0 ns) : restricted to 4.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.400 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C24; Fanout = 3; REG Node = '\count:temp[3]'
            Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 1.400 ns; Loc. = LC2_C13; Fanout = 4; REG Node = '\count:temp[1]'
            Info: Total cell delay = 0.600 ns ( 42.86 % )
            Info: Total interconnect delay = 0.800 ns ( 57.14 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 1.500 ns
                Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2_C13; Fanout = 4; REG Node = '\count:temp[1]'
                Info: Total cell delay = 1.300 ns ( 86.67 % )
                Info: Total interconnect delay = 0.200 ns ( 13.33 % )
            Info: - Longest clock path from clock clk to source register is 1.500 ns
                Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_C24; Fanout = 3; REG Node = '\count:temp[3]'
                Info: Total cell delay = 1.300 ns ( 86.67 % )
                Info: Total interconnect delay = 0.200 ns ( 13.33 % )
        Info: + Micro clock to output delay of source is 0.300 ns
        Info: + Micro setup delay of destination is 0.400 ns
Info: tco from clock clk to destination pin digit[0] through register \count:temp[0] is 6.300 ns
    Info: + Longest clock path from clock clk to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC7_C13; Fanout = 5; REG Node = '\count:temp[0]'
        Info: Total cell delay = 1.300 ns ( 86.67 % )
        Info: Total interconnect delay = 0.200 ns ( 13.33 % )
    Info: + Micro clock to output delay of source is 0.300 ns
    Info: + Longest register to pin delay is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_C13; Fanout = 5; REG Node = '\count:temp[0]'
        Info: 2: + IC(0.700 ns) + CELL(3.800 ns) = 4.500 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'digit[0]'
        Info: Total cell delay = 3.800 ns ( 84.44 % )
        Info: Total interconnect delay = 0.700 ns ( 15.56 % )
Info: Minimum tco from clock clk to destination pin digit[3] through register \count:temp[3] is 6.200 ns
    Info: + Shortest clock path from clock clk to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_C24; Fanout = 3; REG Node = '\count:temp[3]'
        Info: Total cell delay = 1.300 ns ( 86.67 % )
        Info: Total interconnect delay = 0.200 ns ( 13.33 % )
    Info: + Micro clock to output delay of source is 0.300 ns
    Info: + Shortest register to pin delay is 4.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C24; Fanout = 3; REG Node = '\count:temp[3]'
        Info: 2: + IC(0.600 ns) + CELL(3.800 ns) = 4.400 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'digit[3]'
        Info: Total cell delay = 3.800 ns ( 86.36 % )
        Info: Total interconnect delay = 0.600 ns ( 13.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu May 17 12:26:24 2007
    Info: Elapsed time: 00:00:01