jishuqi.vhd

一些很好的FPGA设计实例

--if,wait,cse,loop语句是用于顺序代码的，因此，他们只能在process,function,proceddure中
--if/case 语句在综合时会产生不必要的优先级解码电路
--结构：
--- if codition then assignments;
--- elsif codition then assignments;
---....
---else assignments;
---endif;
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--循环累加的模10计数器，输入信号只有clk，输出是位宽为４的信号digit
--process内部使用了变量temp来实现存储４位输出信号所需的４个d触发器
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library ieee;
use ieee.std_logic_1164.all;
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entity jishuqi is
 port ( clk: in std_logic;
       digit: out integer range 0 to 9);
end jishuqi;
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architecture jishuqi of jishuqi is
 begin 
   count: process (clk)
       variable temp: integer range 0 to 10;
   begin 
      if (clk 'event and clk = '1')then
         temp :=temp+1;
         if (temp =10) then  temp := 0;
         end if;
      end if;
      digit <= temp;
   end process count;
end jishuqi;
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