jishuqi.fit.eqn

一些很好的FPGA设计实例

--\count:temp[3] is \count:temp[3] at LC4_C24
--operation mode is normal

\count:temp[3]_lut_out = \count:temp[3] & (\count:temp[2] $ \count:temp[1] # !\count:temp[0]) # !\count:temp[3] & \count:temp[2] & \count:temp[1] & \count:temp[0];
\count:temp[3] = DFFEA(\count:temp[3]_lut_out, GLOBAL(clk), , , , , );


--\count:temp[2] is \count:temp[2] at LC1_C13
--operation mode is normal

\count:temp[2]_lut_out = \count:temp[2] $ (\count:temp[0] & \count:temp[1]);
\count:temp[2] = DFFEA(\count:temp[2]_lut_out, GLOBAL(clk), , , , , );


--\count:temp[1] is \count:temp[1] at LC2_C13
--operation mode is normal

\count:temp[1]_lut_out = \count:temp[1] & !\count:temp[0] # !\count:temp[1] & \count:temp[0] & (\count:temp[2] # !\count:temp[3]);
\count:temp[1] = DFFEA(\count:temp[1]_lut_out, GLOBAL(clk), , , , , );


--\count:temp[0] is \count:temp[0] at LC7_C13
--operation mode is normal

\count:temp[0]_lut_out = !\count:temp[0];
\count:temp[0] = DFFEA(\count:temp[0]_lut_out, GLOBAL(clk), , , , , );


--clk is clk at PIN_39
--operation mode is input

clk = INPUT();


--digit[3] is digit[3] at PIN_21
--operation mode is output

digit[3] = OUTPUT(\count:temp[3]);


--digit[2] is digit[2] at PIN_19
--operation mode is output

digit[2] = OUTPUT(\count:temp[2]);


--digit[1] is digit[1] at PIN_20
--operation mode is output

digit[1] = OUTPUT(\count:temp[1]);


--digit[0] is digit[0] at PIN_23
--operation mode is output

digit[0] = OUTPUT(\count:temp[0]);