jishuqi.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register \\count:temp\[3\] \\count:temp\[1\] 250.0 MHz Internal " "Info: Clock clk Internal fmax is restricted to 250.0 MHz between source register \\count:temp\[3\] and destination register \\count:temp\[1\]" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.0 ns 2.0 ns 4.0 ns " "Info: fmax restricted to Clock High delay (2.0 ns) plus Clock Low delay (2.0 ns) : restricted to 4.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.400 ns + Longest register register " "Info: + Longest register to register delay is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\count:temp\[3\] 1 REG LC4_C24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C24; Fanout = 3; REG Node = '\\count:temp\[3\]'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "" { \count:temp[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.600 ns) 1.400 ns \\count:temp\[1\] 2 REG LC2_C13 4 " "Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 1.400 ns; Loc. = LC2_C13; Fanout = 4; REG Node = '\\count:temp\[1\]'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.400 ns" { \count:temp[3] \count:temp[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.600 ns 42.86 % " "Info: Total cell delay = 0.600 ns ( 42.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 57.14 % " "Info: Total interconnect delay = 0.800 ns ( 57.14 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.400 ns" { \count:temp[3] \count:temp[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns \\count:temp\[1\] 2 REG LC2_C13 4 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2_C13; Fanout = 4; REG Node = '\\count:temp\[1\]'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "0.200 ns" { clk \count:temp[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk \count:temp[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns \\count:temp\[3\] 2 REG LC4_C24 3 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_C24; Fanout = 3; REG Node = '\\count:temp\[3\]'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "0.200 ns" { clk \count:temp[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk \count:temp[3] } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk \count:temp[1] } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk \count:temp[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.400 ns" { \count:temp[3] \count:temp[1] } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk \count:temp[1] } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk \count:temp[3] } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "" { \count:temp[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk digit\[0\] \\count:temp\[0\] 6.300 ns register " "Info: tco from clock clk to destination pin digit\[0\] through register \\count:temp\[0\] is 6.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns \\count:temp\[0\] 2 REG LC7_C13 5 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC7_C13; Fanout = 5; REG Node = '\\count:temp\[0\]'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "0.200 ns" { clk \count:temp[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk \count:temp[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns + Longest register pin " "Info: + Longest register to pin delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\count:temp\[0\] 1 REG LC7_C13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_C13; Fanout = 5; REG Node = '\\count:temp\[0\]'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "" { \count:temp[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(3.800 ns) 4.500 ns digit\[0\] 2 PIN PIN_23 0 " "Info: 2: + IC(0.700 ns) + CELL(3.800 ns) = 4.500 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'digit\[0\]'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "4.500 ns" { \count:temp[0] digit[0] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 84.44 % " "Info: Total cell delay = 3.800 ns ( 84.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.700 ns 15.56 % " "Info: Total interconnect delay = 0.700 ns ( 15.56 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "4.500 ns" { \count:temp[0] digit[0] } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk \count:temp[0] } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "4.500 ns" { \count:temp[0] digit[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk digit\[3\] \\count:temp\[3\] 6.200 ns register " "Info: Minimum tco from clock clk to destination pin digit\[3\] through register \\count:temp\[3\] is 6.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns \\count:temp\[3\] 2 REG LC4_C24 3 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_C24; Fanout = 3; REG Node = '\\count:temp\[3\]'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "0.200 ns" { clk \count:temp[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk \count:temp[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\count:temp\[3\] 1 REG LC4_C24 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C24; Fanout = 3; REG Node = '\\count:temp\[3\]'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "" { \count:temp[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(3.800 ns) 4.400 ns digit\[3\] 2 PIN PIN_21 0 " "Info: 2: + IC(0.600 ns) + CELL(3.800 ns) = 4.400 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'digit\[3\]'" {  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "4.400 ns" { \count:temp[3] digit[3] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/6.2模10计数器#1/jishuqi.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 86.36 % " "Info: Total cell delay = 3.800 ns ( 86.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 13.64 % " "Info: Total interconnect delay = 0.600 ns ( 13.64 % )" {  } {  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "4.400 ns" { \count:temp[3] digit[3] } "NODE_NAME" } } }  } 0}  } { { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk \count:temp[3] } "NODE_NAME" } } } { "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" "" "" { Report "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi_cmp.qrpt" Compiler "jishuqi" "UNKNOWN" "V1" "D:/VHDL数字逻辑教程/6.2模10计数器#1/db/jishuqi.quartus_db" { Floorplan "" "" "4.400 ns" { \count:temp[3] digit[3] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 12:26:24 2007 " "Info: Processing ended: Thu May 17 12:26:24 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}