cdu24.tan.rpt

一些很好的FPGA设计实例

        Info: Total cell delay = 1.399 ns ( 57.31 % )
        Info: Total interconnect delay = 1.042 ns ( 42.69 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk1" to destination register is 7.001 ns
            Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_U16; Fanout = 1; CLK Node = 'clk1'
            Info: 2: + IC(1.631 ns) + CELL(0.075 ns) = 2.793 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.001 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2[3]'
            Info: Total cell delay = 1.704 ns ( 24.34 % )
            Info: Total interconnect delay = 5.297 ns ( 75.66 % )
        Info: - Longest clock path from clock "clk1" to source register is 7.001 ns
            Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_U16; Fanout = 1; CLK Node = 'clk1'
            Info: 2: + IC(1.631 ns) + CELL(0.075 ns) = 2.793 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.001 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1[1]'
            Info: Total cell delay = 1.704 ns ( 24.34 % )
            Info: Total interconnect delay = 5.297 ns ( 75.66 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: Clock "sa" has Internal fmax of 383.58 MHz between source register "out1[1]" and destination register "out2[3]" (period= 2.607 ns)
    Info: + Longest register to register delay is 2.441 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1[1]'
        Info: 2: + IC(0.398 ns) + CELL(0.366 ns) = 0.764 ns; Loc. = LC_X9_Y18_N6; Fanout = 1; COMB Node = 'process0~54'
        Info: 3: + IC(0.324 ns) + CELL(0.075 ns) = 1.163 ns; Loc. = LC_X9_Y18_N5; Fanout = 4; COMB Node = 'process0~1'
        Info: 4: + IC(0.320 ns) + CELL(0.341 ns) = 1.824 ns; Loc. = LC_X9_Y18_N1; Fanout = 2; COMB Node = 'out2[0]~52COUT1_57'
        Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.884 ns; Loc. = LC_X9_Y18_N2; Fanout = 2; COMB Node = 'out2[1]~53COUT1'
        Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 1.944 ns; Loc. = LC_X9_Y18_N3; Fanout = 1; COMB Node = 'out2[2]~54COUT1_58'
        Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.441 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2[3]'
        Info: Total cell delay = 1.399 ns ( 57.31 % )
        Info: Total interconnect delay = 1.042 ns ( 42.69 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "sa" to destination register is 7.268 ns
            Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_T16; Fanout = 2; CLK Node = 'sa'
            Info: 2: + IC(1.790 ns) + CELL(0.183 ns) = 3.060 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.268 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2[3]'
            Info: Total cell delay = 1.812 ns ( 24.93 % )
            Info: Total interconnect delay = 5.456 ns ( 75.07 % )
        Info: - Longest clock path from clock "sa" to source register is 7.268 ns
            Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_T16; Fanout = 2; CLK Node = 'sa'
            Info: 2: + IC(1.790 ns) + CELL(0.183 ns) = 3.060 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.268 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1[1]'
            Info: Total cell delay = 1.812 ns ( 24.93 % )
            Info: Total interconnect delay = 5.456 ns ( 75.07 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: Clock "clk2" has Internal fmax of 383.58 MHz between source register "out1[1]" and destination register "out2[3]" (period= 2.607 ns)
    Info: + Longest register to register delay is 2.441 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1[1]'
        Info: 2: + IC(0.398 ns) + CELL(0.366 ns) = 0.764 ns; Loc. = LC_X9_Y18_N6; Fanout = 1; COMB Node = 'process0~54'
        Info: 3: + IC(0.324 ns) + CELL(0.075 ns) = 1.163 ns; Loc. = LC_X9_Y18_N5; Fanout = 4; COMB Node = 'process0~1'
        Info: 4: + IC(0.320 ns) + CELL(0.341 ns) = 1.824 ns; Loc. = LC_X9_Y18_N1; Fanout = 2; COMB Node = 'out2[0]~52COUT1_57'
        Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.884 ns; Loc. = LC_X9_Y18_N2; Fanout = 2; COMB Node = 'out2[1]~53COUT1'
        Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 1.944 ns; Loc. = LC_X9_Y18_N3; Fanout = 1; COMB Node = 'out2[2]~54COUT1_58'
        Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.441 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2[3]'
        Info: Total cell delay = 1.399 ns ( 57.31 % )
        Info: Total interconnect delay = 1.042 ns ( 42.69 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk2" to destination register is 7.331 ns
            Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_V17; Fanout = 1; CLK Node = 'clk2'
            Info: 2: + IC(1.756 ns) + CELL(0.280 ns) = 3.123 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.331 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2[3]'
            Info: Total cell delay = 1.909 ns ( 26.04 % )
            Info: Total interconnect delay = 5.422 ns ( 73.96 % )
        Info: - Longest clock path from clock "clk2" to source register is 7.331 ns
            Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_V17; Fanout = 1; CLK Node = 'clk2'
            Info: 2: + IC(1.756 ns) + CELL(0.280 ns) = 3.123 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.331 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1[1]'
            Info: Total cell delay = 1.909 ns ( 26.04 % )
            Info: Total interconnect delay = 5.422 ns ( 73.96 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock "clk2" to destination pin "co" through register "cay" is 12.559 ns
    Info: + Longest clock path from clock "clk2" to source register is 7.331 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_V17; Fanout = 1; CLK Node = 'clk2'
        Info: 2: + IC(1.756 ns) + CELL(0.280 ns) = 3.123 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'
        Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.331 ns; Loc. = LC_X8_Y18_N6; Fanout = 1; REG Node = 'cay'
        Info: Total cell delay = 1.909 ns ( 26.04 % )
        Info: Total interconnect delay = 5.422 ns ( 73.96 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 5.072 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y18_N6; Fanout = 1; REG Node = 'cay'
        Info: 2: + IC(0.386 ns) + CELL(0.280 ns) = 0.666 ns; Loc. = LC_X8_Y18_N8; Fanout = 1; COMB Node = 'co~9'
        Info: 3: + IC(2.002 ns) + CELL(2.404 ns) = 5.072 ns; Loc. = PIN_Y15; Fanout = 0; PIN Node = 'co'
        Info: Total cell delay = 2.684 ns ( 52.92 % )
        Info: Total interconnect delay = 2.388 ns ( 47.08 % )
Info: Longest tpd from source pin "sa" to destination pin "co" is 10.071 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_T16; Fanout = 2; CLK Node = 'sa'
    Info: 2: + IC(4.503 ns) + CELL(0.075 ns) = 5.665 ns; Loc. = LC_X8_Y18_N8; Fanout = 1; COMB Node = 'co~9'
    Info: 3: + IC(2.002 ns) + CELL(2.404 ns) = 10.071 ns; Loc. = PIN_Y15; Fanout = 0; PIN Node = 'co'
    Info: Total cell delay = 3.566 ns ( 35.41 % )
    Info: Total interconnect delay = 6.505 ns ( 64.59 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Oct 10 22:47:13 2007
    Info: Elapsed time: 00:00:01