control.tan.rpt

一些很好的FPGA设计实例

+-------------------------------------------------------------+
; tpd                                                         ;
+-------+-------------------+-----------------+---------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From    ; To  ;
+-------+-------------------+-----------------+---------+-----+
; N/A   ; None              ; 10.338 ns       ; q2[3]   ; bee ;
; N/A   ; None              ; 10.221 ns       ; q2[4]   ; bee ;
; N/A   ; None              ; 10.069 ns       ; q1[4]   ; bee ;
; N/A   ; None              ; 9.968 ns        ; q1[3]   ; bee ;
; N/A   ; None              ; 9.801 ns        ; q2[0]   ; bee ;
; N/A   ; None              ; 9.792 ns        ; q2[6]   ; bee ;
; N/A   ; None              ; 9.772 ns        ; q1[7]   ; bee ;
; N/A   ; None              ; 9.660 ns        ; q1[0]   ; bee ;
; N/A   ; None              ; 9.634 ns        ; q1[1]   ; bee ;
; N/A   ; None              ; 9.592 ns        ; q1[6]   ; bee ;
; N/A   ; None              ; 9.390 ns        ; q2[2]   ; bee ;
; N/A   ; None              ; 9.385 ns        ; q1[5]   ; bee ;
; N/A   ; None              ; 9.284 ns        ; clk500  ; bee ;
; N/A   ; None              ; 9.275 ns        ; q2[1]   ; bee ;
; N/A   ; None              ; 9.186 ns        ; q2[7]   ; bee ;
; N/A   ; None              ; 9.172 ns        ; q1[2]   ; bee ;
; N/A   ; None              ; 9.062 ns        ; q2[5]   ; bee ;
; N/A   ; None              ; 7.434 ns        ; clk1024 ; bee ;
+-------+-------------------+-----------------+---------+-----+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -1.470 ns ; sb   ; setb~reg0 ; clk1024  ;
; N/A           ; None        ; -1.749 ns ; sc   ; clrc~reg0 ; clk1024  ;
; N/A           ; None        ; -2.631 ns ; sa   ; seta~reg0 ; clk1024  ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Oct 10 21:54:58 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off control -c control --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "clk1024" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "count[1]" and destination register "count[1]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.717 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y10_N7; Fanout = 2; REG Node = 'count[1]'
            Info: 2: + IC(0.398 ns) + CELL(0.319 ns) = 0.717 ns; Loc. = LC_X52_Y10_N7; Fanout = 2; REG Node = 'count[1]'
            Info: Total cell delay = 0.319 ns ( 44.49 % )
            Info: Total interconnect delay = 0.398 ns ( 55.51 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.916 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 2; CLK Node = 'clk'
                Info: 2: + IC(1.649 ns) + CELL(0.542 ns) = 2.916 ns; Loc. = LC_X52_Y10_N7; Fanout = 2; REG Node = 'count[1]'
                Info: Total cell delay = 1.267 ns ( 43.45 % )
                Info: Total interconnect delay = 1.649 ns ( 56.55 % )
            Info: - Longest clock path from clock "clk" to source register is 2.916 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 2; CLK Node = 'clk'
                Info: 2: + IC(1.649 ns) + CELL(0.542 ns) = 2.916 ns; Loc. = LC_X52_Y10_N7; Fanout = 2; REG Node = 'count[1]'
                Info: Total cell delay = 1.267 ns ( 43.45 % )
                Info: Total interconnect delay = 1.649 ns ( 56.55 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: No valid register-to-register data paths exist for clock "clk1024"
Info: tsu for register "seta~reg0" (data pin = "sa", clock pin = "clk1024") is 2.741 ns
    Info: + Longest pin to register delay is 5.695 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F8; Fanout = 1; PIN Node = 'sa'
        Info: 2: + IC(4.523 ns) + CELL(0.085 ns) = 5.695 ns; Loc. = LC_X41_Y5_N2; Fanout = 1; REG Node = 'seta~reg0'
        Info: Total cell delay = 1.172 ns ( 20.58 % )
        Info: Total interconnect delay = 4.523 ns ( 79.42 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk1024" to destination register is 2.964 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk1024'
        Info: 2: + IC(1.594 ns) + CELL(0.542 ns) = 2.964 ns; Loc. = LC_X41_Y5_N2; Fanout = 1; REG Node = 'seta~reg0'
        Info: Total cell delay = 1.370 ns ( 46.22 % )
        Info: Total interconnect delay = 1.594 ns ( 53.78 % )
Info: tco from clock "clk1024" to destination pin "clrc" through register "clrc~reg0" is 7.000 ns
    Info: + Longest clock path from clock "clk1024" to source register is 2.998 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk1024'
        Info: 2: + IC(1.628 ns) + CELL(0.542 ns) = 2.998 ns; Loc. = LC_X25_Y1_N2; Fanout = 1; REG Node = 'clrc~reg0'
        Info: Total cell delay = 1.370 ns ( 45.70 % )
        Info: Total interconnect delay = 1.628 ns ( 54.30 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.846 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y1_N2; Fanout = 1; REG Node = 'clrc~reg0'
        Info: 2: + IC(1.159 ns) + CELL(2.687 ns) = 3.846 ns; Loc. = PIN_AB12; Fanout = 0; PIN Node = 'clrc'
        Info: Total cell delay = 2.687 ns ( 69.86 % )
        Info: Total interconnect delay = 1.159 ns ( 30.14 % )
Info: Longest tpd from source pin "q2[3]" to destination pin "bee" is 10.338 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AB18; Fanout = 2; PIN Node = 'q2[3]'
    Info: 2: + IC(3.925 ns) + CELL(0.366 ns) = 5.378 ns; Loc. = LC_X7_Y1_N7; Fanout = 1; COMB Node = 'bee~350'
    Info: 3: + IC(0.325 ns) + CELL(0.366 ns) = 6.069 ns; Loc. = LC_X7_Y1_N8; Fanout = 1; COMB Node = 'bee~351'
    Info: 4: + IC(0.470 ns) + CELL(0.280 ns) = 6.819 ns; Loc. = LC_X7_Y1_N6; Fanout = 1; COMB Node = 'bee~355'
    Info: 5: + IC(1.115 ns) + CELL(2.404 ns) = 10.338 ns; Loc. = PIN_V16; Fanout = 0; PIN Node = 'bee'
    Info: Total cell delay = 4.503 ns ( 43.56 % )
    Info: Total interconnect delay = 5.835 ns ( 56.44 % )
Info: th for register "setb~reg0" (data pin = "sb", clock pin = "clk1024") is -1.470 ns
    Info: + Longest clock path from clock "clk1024" to destination register is 2.928 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk1024'
        Info: 2: + IC(1.558 ns) + CELL(0.542 ns) = 2.928 ns; Loc. = LC_X1_Y27_N0; Fanout = 1; REG Node = 'setb~reg0'
        Info: Total cell delay = 1.370 ns ( 46.79 % )
        Info: Total interconnect delay = 1.558 ns ( 53.21 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.498 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G20; Fanout = 1; PIN Node = 'sb'
        Info: 2: + IC(3.179 ns) + CELL(0.085 ns) = 4.498 ns; Loc. = LC_X1_Y27_N0; Fanout = 1; REG Node = 'setb~reg0'
        Info: Total cell delay = 1.319 ns ( 29.32 % )
        Info: Total interconnect delay = 3.179 ns ( 70.68 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Oct 10 21:54:59 2007
    Info: Elapsed time: 00:00:02