control.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_TPD_RESULT" "q2\[3\] bee 10.338 ns Longest " "Info: Longest tpd from source pin \"q2\[3\]\" to destination pin \"bee\" is 10.338 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns q2\[3\] 1 PIN PIN_AB18 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AB18; Fanout = 2; PIN Node = 'q2\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { q2[3] } "NODE_NAME" } } { "control.vhd" "" { Text "E:/多功能数字钟的设计/control/control.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.925 ns) + CELL(0.366 ns) 5.378 ns bee~350 2 COMB LC_X7_Y1_N7 1 " "Info: 2: + IC(3.925 ns) + CELL(0.366 ns) = 5.378 ns; Loc. = LC_X7_Y1_N7; Fanout = 1; COMB Node = 'bee~350'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.291 ns" { q2[3] bee~350 } "NODE_NAME" } } { "control.vhd" "" { Text "E:/多功能数字钟的设计/control/control.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.366 ns) 6.069 ns bee~351 3 COMB LC_X7_Y1_N8 1 " "Info: 3: + IC(0.325 ns) + CELL(0.366 ns) = 6.069 ns; Loc. = LC_X7_Y1_N8; Fanout = 1; COMB Node = 'bee~351'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.691 ns" { bee~350 bee~351 } "NODE_NAME" } } { "control.vhd" "" { Text "E:/多功能数字钟的设计/control/control.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.280 ns) 6.819 ns bee~355 4 COMB LC_X7_Y1_N6 1 " "Info: 4: + IC(0.470 ns) + CELL(0.280 ns) = 6.819 ns; Loc. = LC_X7_Y1_N6; Fanout = 1; COMB Node = 'bee~355'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.750 ns" { bee~351 bee~355 } "NODE_NAME" } } { "control.vhd" "" { Text "E:/多功能数字钟的设计/control/control.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(2.404 ns) 10.338 ns bee 5 PIN PIN_V16 0 " "Info: 5: + IC(1.115 ns) + CELL(2.404 ns) = 10.338 ns; Loc. = PIN_V16; Fanout = 0; PIN Node = 'bee'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.519 ns" { bee~355 bee } "NODE_NAME" } } { "control.vhd" "" { Text "E:/多功能数字钟的设计/control/control.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.503 ns ( 43.56 % ) " "Info: Total cell delay = 4.503 ns ( 43.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.835 ns ( 56.44 % ) " "Info: Total interconnect delay = 5.835 ns ( 56.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.338 ns" { q2[3] bee~350 bee~351 bee~355 bee } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.338 ns" { q2[3] q2[3]~out0 bee~350 bee~351 bee~355 bee } { 0.000ns 0.000ns 3.925ns 0.325ns 0.470ns 1.115ns } { 0.000ns 1.087ns 0.366ns 0.366ns 0.280ns 2.404ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "setb~reg0 sb clk1024 -1.470 ns register " "Info: th for register \"setb~reg0\" (data pin = \"sb\", clock pin = \"clk1024\") is -1.470 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1024 destination 2.928 ns + Longest register " "Info: + Longest clock path from clock \"clk1024\" to destination register is 2.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk1024 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk1024'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1024 } "NODE_NAME" } } { "control.vhd" "" { Text "E:/多功能数字钟的设计/control/control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.558 ns) + CELL(0.542 ns) 2.928 ns setb~reg0 2 REG LC_X1_Y27_N0 1 " "Info: 2: + IC(1.558 ns) + CELL(0.542 ns) = 2.928 ns; Loc. = LC_X1_Y27_N0; Fanout = 1; REG Node = 'setb~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { clk1024 setb~reg0 } "NODE_NAME" } } { "control.vhd" "" { Text "E:/多功能数字钟的设计/control/control.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.79 % ) " "Info: Total cell delay = 1.370 ns ( 46.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.558 ns ( 53.21 % ) " "Info: Total interconnect delay = 1.558 ns ( 53.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.928 ns" { clk1024 setb~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.928 ns" { clk1024 clk1024~out0 setb~reg0 } { 0.000ns 0.000ns 1.558ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "control.vhd" "" { Text "E:/多功能数字钟的设计/control/control.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.498 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns sb 1 PIN PIN_G20 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G20; Fanout = 1; PIN Node = 'sb'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sb } "NODE_NAME" } } { "control.vhd" "" { Text "E:/多功能数字钟的设计/control/control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.179 ns) + CELL(0.085 ns) 4.498 ns setb~reg0 2 REG LC_X1_Y27_N0 1 " "Info: 2: + IC(3.179 ns) + CELL(0.085 ns) = 4.498 ns; Loc. = LC_X1_Y27_N0; Fanout = 1; REG Node = 'setb~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.264 ns" { sb setb~reg0 } "NODE_NAME" } } { "control.vhd" "" { Text "E:/多功能数字钟的设计/control/control.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 29.32 % ) " "Info: Total cell delay = 1.319 ns ( 29.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.179 ns ( 70.68 % ) " "Info: Total interconnect delay = 3.179 ns ( 70.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.498 ns" { sb setb~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.498 ns" { sb sb~out0 setb~reg0 } { 0.000ns 0.000ns 3.179ns } { 0.000ns 1.234ns 0.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.928 ns" { clk1024 setb~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.928 ns" { clk1024 clk1024~out0 setb~reg0 } { 0.000ns 0.000ns 1.558ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.498 ns" { sb setb~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.498 ns" { sb sb~out0 setb~reg0 } { 0.000ns 0.000ns 3.179ns } { 0.000ns 1.234ns 0.085ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 10 21:54:59 2007 " "Info: Processing ended: Wed Oct 10 21:54:59 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}