control.vhd

一些很好的FPGA设计实例

--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--******************************************************

ENTITY control IS
	PORT(
          	clk,clk1024,clk500,sa,sb,sc: in std_logic;--clk 2HZ ;ckl1024 1024HZ;
--ckl500 500HZ;sa,sb,sc 调时间按键
            q1: in std_logic_vector(7 downto 0);--秒钟			        
            q2: in std_logic_vector(7 downto 0);--分钟	  
            bee,clks,seta,setb,clrc : out std_logic
--bee 蜂鸣器输出，clks 1hz输出，seta,setb,clrc  分别为sa,sb,sc是消抖输出
		);
END control;

--*******************************************************

ARCHITECTURE aa OF control IS
	SIGNAL count : STD_LOGIC_VECTOR (1 DOWNTO 0) ;
BEGIN
clk_label:process(clk)
    begin
    if clk'event and clk ='1' then
       count <= count +1;
    end if;
end process clk_label;

clk1024_label:process(clk1024)
    begin
    if clk1024'event and clk1024 ='1' then--1024HZ频率采样对输入按键消抖
    seta <= sa;
    setb <= sb;
    clrc <= sc;
    end if;
end process clk1024_label; 
clks <= count(1);--count为输入为2HZ时钟的2分频,响应clks为1HZ
bee <= CLK500 when q2(7 downto 0)="01011001" and q1(7 downto 4)="0101" and q1(0)='0' 
       else
    clk1024 when q2(7 downto 0) & q1(7 downto 0)="00000000000000"
       else  '0';
--前5声报时由500HZ驱动,整点报失由1024HZ驱动
end aa;