cdu60s.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 51 行

--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--******************************************************

ENTITY cdu60s IS-- 秒钟显示模块
	PORT(
          	clk1,clr: in std_logic;--clk1输入1HZ时钟,clr清零信号
            co: out std_logic;--进位输出
            m:  out std_logic_vector(7 downto 0)--秒钟显示输出			        
		);
END cdu60s;

--*******************************************************

ARCHITECTURE aa OF cdu60s IS
	SIGNAL out1,out2 : integer range 0 to 9;
	SIGNAL out3,out4 : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
	SIGNAL clk : STD_LOGIC;
BEGIN
process(clk1)
    begin
    if clr='1' then 
       out1<=0;
       out2<=0;--异步清零
    elsif clk1'event and clk1 ='1' then
       if (out2<=5)and(out1<=9)then --摸59计数
       out1<=0;
       out2<=0;
       co<='1';  
       else      
       out1 <=  out1 +1;
       co<='0';
          if out1 =9 and out2 /=5 then 
             out1<=0;
             out2 <=  out2 +1;
             co<='0'; 
         end if;
       end if;
    end if;

out3 <= conv_std_logic_vector(out1,4);--进制转换
out3 <= conv_std_logic_vector(out2,4);
m <= out4& out3;
end process;
end aa;