📄 cdu60s.tan.rpt
字号:
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out2[0] ; clk1 ; clk1 ; None ; None ; 2.053 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[0] ; out1[2] ; clk1 ; clk1 ; None ; None ; 2.024 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; out1[3] ; clk1 ; clk1 ; None ; None ; 2.016 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out1[2] ; clk1 ; clk1 ; None ; None ; 2.012 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out1[3] ; clk1 ; clk1 ; None ; None ; 2.009 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[1] ; out1[2] ; clk1 ; clk1 ; None ; None ; 1.988 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[0] ; out2[0] ; clk1 ; clk1 ; None ; None ; 1.983 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[0] ; out1[3] ; clk1 ; clk1 ; None ; None ; 1.939 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[1] ; co~reg0 ; clk1 ; clk1 ; None ; None ; 1.914 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[1] ; out1[3] ; clk1 ; clk1 ; None ; None ; 1.912 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[1] ; out1[1] ; clk1 ; clk1 ; None ; None ; 1.911 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[1] ; out1[0] ; clk1 ; clk1 ; None ; None ; 1.908 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[0] ; out2[0] ; clk1 ; clk1 ; None ; None ; 1.902 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; co~reg0 ; clk1 ; clk1 ; None ; None ; 1.893 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; out1[1] ; clk1 ; clk1 ; None ; None ; 1.890 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; out1[2] ; clk1 ; clk1 ; None ; None ; 1.889 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; out1[0] ; clk1 ; clk1 ; None ; None ; 1.887 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[0] ; out1[2] ; clk1 ; clk1 ; None ; None ; 1.861 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[0] ; out1[3] ; clk1 ; clk1 ; None ; None ; 1.858 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out1[1] ; clk1 ; clk1 ; None ; None ; 1.646 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; co~reg0 ; clk1 ; clk1 ; None ; None ; 1.626 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out1[0] ; clk1 ; clk1 ; None ; None ; 1.620 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[0] ; out1[1] ; clk1 ; clk1 ; None ; None ; 1.576 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[0] ; out1[1] ; clk1 ; clk1 ; None ; None ; 1.495 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; co~reg0 ; co~reg0 ; clk1 ; clk1 ; None ; None ; 0.931 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[0] ; out1[0] ; clk1 ; clk1 ; None ; None ; 0.625 ns ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+---------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+---------+----------+
; N/A ; None ; -0.029 ns ; clr ; co~reg0 ; clk1 ;
+-------+--------------+------------+------+---------+----------+
+-----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------+------+------------+
; N/A ; None ; 6.977 ns ; co~reg0 ; co ; clk1 ;
; N/A ; None ; 6.757 ns ; out2[2] ; m[2] ; clk1 ;
; N/A ; None ; 6.756 ns ; out2[3] ; m[3] ; clk1 ;
; N/A ; None ; 6.754 ns ; out2[1] ; m[1] ; clk1 ;
; N/A ; None ; 6.748 ns ; out2[0] ; m[0] ; clk1 ;
+-------+--------------+------------+---------+------+------------+
+---------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+---------+----------+
; N/A ; None ; 0.139 ns ; clr ; co~reg0 ; clk1 ;
+---------------+-------------+-----------+------+---------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Wed Oct 10 22:27:16 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cdu60s -c cdu60s --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk1" is an undefined clock
Info: Clock "clk1" has Internal fmax of 367.78 MHz between source register "out2[3]" and destination register "out2[3]" (period= 2.719 ns)
Info: + Longest register to register delay is 2.553 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y27_N8; Fanout = 4; REG Node = 'out2[3]'
Info: 2: + IC(0.410 ns) + CELL(0.366 ns) = 0.776 ns; Loc. = LC_X13_Y27_N3; Fanout = 1; COMB Node = 'Equal1~28'
Info: 3: + IC(0.330 ns) + CELL(0.183 ns) = 1.289 ns; Loc. = LC_X13_Y27_N1; Fanout = 6; COMB Node = 'process0~1'
Info: 4: + IC(0.306 ns) + CELL(0.341 ns) = 1.936 ns; Loc. = LC_X13_Y27_N5; Fanout = 2; COMB Node = 'out2[0]~45COUT1_50'
Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.996 ns; Loc. = LC_X13_Y27_N6; Fanout = 2; COMB Node = 'out2[1]~46COUT1'
Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 2.056 ns; Loc. = LC_X13_Y27_N7; Fanout = 1; COMB Node = 'out2[2]~47COUT1_51'
Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.553 ns; Loc. = LC_X13_Y27_N8; Fanout = 4; REG Node = 'out2[3]'
Info: Total cell delay = 1.507 ns ( 59.03 % )
Info: Total interconnect delay = 1.046 ns ( 40.97 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk1" to destination register is 2.930 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'clk1'
Info: 2: + IC(1.560 ns) + CELL(0.542 ns) = 2.930 ns; Loc. = LC_X13_Y27_N8; Fanout = 4; REG Node = 'out2[3]'
Info: Total cell delay = 1.370 ns ( 46.76 % )
Info: Total interconnect delay = 1.560 ns ( 53.24 % )
Info: - Longest clock path from clock "clk1" to source register is 2.930 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'clk1'
Info: 2: + IC(1.560 ns) + CELL(0.542 ns) = 2.930 ns; Loc. = LC_X13_Y27_N8; Fanout = 4; REG Node = 'out2[3]'
Info: Total cell delay = 1.370 ns ( 46.76 % )
Info: Total interconnect delay = 1.560 ns ( 53.24 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "co~reg0" (data pin = "clr", clock pin = "clk1") is -0.029 ns
Info: + Longest pin to register delay is 2.891 ns
Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 9; PIN Node = 'clr'
Info: 2: + IC(1.943 ns) + CELL(0.223 ns) = 2.891 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'
Info: Total cell delay = 0.948 ns ( 32.79 % )
Info: Total interconnect delay = 1.943 ns ( 67.21 % )
Info: + Micro setup delay of destination is 0.010 ns
Info: - Shortest clock path from clock "clk1" to destination register is 2.930 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'clk1'
Info: 2: + IC(1.560 ns) + CELL(0.542 ns) = 2.930 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'
Info: Total cell delay = 1.370 ns ( 46.76 % )
Info: Total interconnect delay = 1.560 ns ( 53.24 % )
Info: tco from clock "clk1" to destination pin "co" through register "co~reg0" is 6.977 ns
Info: + Longest clock path from clock "clk1" to source register is 2.930 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'clk1'
Info: 2: + IC(1.560 ns) + CELL(0.542 ns) = 2.930 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'
Info: Total cell delay = 1.370 ns ( 46.76 % )
Info: Total interconnect delay = 1.560 ns ( 53.24 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Longest register to pin delay is 3.891 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'
Info: 2: + IC(1.487 ns) + CELL(2.404 ns) = 3.891 ns; Loc. = PIN_D15; Fanout = 0; PIN Node = 'co'
Info: Total cell delay = 2.404 ns ( 61.78 % )
Info: Total interconnect delay = 1.487 ns ( 38.22 % )
Info: th for register "co~reg0" (data pin = "clr", clock pin = "clk1") is 0.139 ns
Info: + Longest clock path from clock "clk1" to destination register is 2.930 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'clk1'
Info: 2: + IC(1.560 ns) + CELL(0.542 ns) = 2.930 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'
Info: Total cell delay = 1.370 ns ( 46.76 % )
Info: Total interconnect delay = 1.560 ns ( 53.24 % )
Info: + Micro hold delay of destination is 0.100 ns
Info: - Shortest pin to register delay is 2.891 ns
Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 9; PIN Node = 'clr'
Info: 2: + IC(1.943 ns) + CELL(0.223 ns) = 2.891 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'
Info: Total cell delay = 0.948 ns ( 32.79 % )
Info: Total interconnect delay = 1.943 ns ( 67.21 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Wed Oct 10 22:27:16 2007
Info: Elapsed time: 00:00:01
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