cdu60.tan.summary

来自「一些很好的FPGA设计实例」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.863 ns
From           : cay
To             : co
From Clock     : clk1
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 7.933 ns
From           : ss
To             : co
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk2'
Slack          : N/A
Required Time  : None
Actual Time    : 351.00 MHz ( period = 2.849 ns )
From           : out1[1]
To             : out2[3]
From Clock     : clk2
To Clock       : clk2
Failed Paths   : 0

Type           : Clock Setup: 'clk1'
Slack          : N/A
Required Time  : None
Actual Time    : 351.00 MHz ( period = 2.849 ns )
From           : out1[1]
To             : out2[3]
From Clock     : clk1
To Clock       : clk1
Failed Paths   : 0

Type           : Clock Setup: 'ss'
Slack          : N/A
Required Time  : None
Actual Time    : 351.00 MHz ( period = 2.849 ns )
From           : out1[1]
To             : out2[3]
From Clock     : ss
To Clock       : ss
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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