cdu60.tan.rpt

一些很好的FPGA设计实例

        Info: + Shortest clock path from clock "ss" to destination register is 5.033 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L22; Fanout = 2; CLK Node = 'ss'
            Info: 2: + IC(0.598 ns) + CELL(0.075 ns) = 1.398 ns; Loc. = LC_X1_Y19_N2; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.093 ns) + CELL(0.542 ns) = 5.033 ns; Loc. = LC_X35_Y29_N4; Fanout = 5; REG Node = 'out2[3]'
            Info: Total cell delay = 1.342 ns ( 26.66 % )
            Info: Total interconnect delay = 3.691 ns ( 73.34 % )
        Info: - Longest clock path from clock "ss" to source register is 5.033 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L22; Fanout = 2; CLK Node = 'ss'
            Info: 2: + IC(0.598 ns) + CELL(0.075 ns) = 1.398 ns; Loc. = LC_X1_Y19_N2; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.093 ns) + CELL(0.542 ns) = 5.033 ns; Loc. = LC_X35_Y29_N9; Fanout = 4; REG Node = 'out1[1]'
            Info: Total cell delay = 1.342 ns ( 26.66 % )
            Info: Total interconnect delay = 3.691 ns ( 73.34 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: Clock "clk1" has Internal fmax of 351.0 MHz between source register "out1[1]" and destination register "out2[3]" (period= 2.849 ns)
    Info: + Longest register to register delay is 2.683 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y29_N9; Fanout = 4; REG Node = 'out1[1]'
        Info: 2: + IC(0.393 ns) + CELL(0.280 ns) = 0.673 ns; Loc. = LC_X35_Y29_N5; Fanout = 3; COMB Node = 'process0~51'
        Info: 3: + IC(0.344 ns) + CELL(0.183 ns) = 1.200 ns; Loc. = LC_X35_Y29_N8; Fanout = 6; COMB Node = 'process0~1'
        Info: 4: + IC(0.525 ns) + CELL(0.341 ns) = 2.066 ns; Loc. = LC_X35_Y29_N1; Fanout = 2; COMB Node = 'out2[0]~45COUT1_50'
        Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 2.126 ns; Loc. = LC_X35_Y29_N2; Fanout = 2; COMB Node = 'out2[1]~46COUT1'
        Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 2.186 ns; Loc. = LC_X35_Y29_N3; Fanout = 1; COMB Node = 'out2[2]~47COUT1_51'
        Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.683 ns; Loc. = LC_X35_Y29_N4; Fanout = 5; REG Node = 'out2[3]'
        Info: Total cell delay = 1.421 ns ( 52.96 % )
        Info: Total interconnect delay = 1.262 ns ( 47.04 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk1" to destination register is 5.257 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 1; CLK Node = 'clk1'
            Info: 2: + IC(0.611 ns) + CELL(0.183 ns) = 1.622 ns; Loc. = LC_X1_Y19_N2; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.093 ns) + CELL(0.542 ns) = 5.257 ns; Loc. = LC_X35_Y29_N4; Fanout = 5; REG Node = 'out2[3]'
            Info: Total cell delay = 1.553 ns ( 29.54 % )
            Info: Total interconnect delay = 3.704 ns ( 70.46 % )
        Info: - Longest clock path from clock "clk1" to source register is 5.257 ns
            Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 1; CLK Node = 'clk1'
            Info: 2: + IC(0.611 ns) + CELL(0.183 ns) = 1.622 ns; Loc. = LC_X1_Y19_N2; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.093 ns) + CELL(0.542 ns) = 5.257 ns; Loc. = LC_X35_Y29_N9; Fanout = 4; REG Node = 'out1[1]'
            Info: Total cell delay = 1.553 ns ( 29.54 % )
            Info: Total interconnect delay = 3.704 ns ( 70.46 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: Clock "clk2" has Internal fmax of 351.0 MHz between source register "out1[1]" and destination register "out2[3]" (period= 2.849 ns)
    Info: + Longest register to register delay is 2.683 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y29_N9; Fanout = 4; REG Node = 'out1[1]'
        Info: 2: + IC(0.393 ns) + CELL(0.280 ns) = 0.673 ns; Loc. = LC_X35_Y29_N5; Fanout = 3; COMB Node = 'process0~51'
        Info: 3: + IC(0.344 ns) + CELL(0.183 ns) = 1.200 ns; Loc. = LC_X35_Y29_N8; Fanout = 6; COMB Node = 'process0~1'
        Info: 4: + IC(0.525 ns) + CELL(0.341 ns) = 2.066 ns; Loc. = LC_X35_Y29_N1; Fanout = 2; COMB Node = 'out2[0]~45COUT1_50'
        Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 2.126 ns; Loc. = LC_X35_Y29_N2; Fanout = 2; COMB Node = 'out2[1]~46COUT1'
        Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 2.186 ns; Loc. = LC_X35_Y29_N3; Fanout = 1; COMB Node = 'out2[2]~47COUT1_51'
        Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.683 ns; Loc. = LC_X35_Y29_N4; Fanout = 5; REG Node = 'out2[3]'
        Info: Total cell delay = 1.421 ns ( 52.96 % )
        Info: Total interconnect delay = 1.262 ns ( 47.04 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk2" to destination register is 5.221 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L21; Fanout = 1; CLK Node = 'clk2'
            Info: 2: + IC(0.581 ns) + CELL(0.280 ns) = 1.586 ns; Loc. = LC_X1_Y19_N2; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.093 ns) + CELL(0.542 ns) = 5.221 ns; Loc. = LC_X35_Y29_N4; Fanout = 5; REG Node = 'out2[3]'
            Info: Total cell delay = 1.547 ns ( 29.63 % )
            Info: Total interconnect delay = 3.674 ns ( 70.37 % )
        Info: - Longest clock path from clock "clk2" to source register is 5.221 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L21; Fanout = 1; CLK Node = 'clk2'
            Info: 2: + IC(0.581 ns) + CELL(0.280 ns) = 1.586 ns; Loc. = LC_X1_Y19_N2; Fanout = 9; COMB Node = 'clk~7'
            Info: 3: + IC(3.093 ns) + CELL(0.542 ns) = 5.221 ns; Loc. = LC_X35_Y29_N9; Fanout = 4; REG Node = 'out1[1]'
            Info: Total cell delay = 1.547 ns ( 29.63 % )
            Info: Total interconnect delay = 3.674 ns ( 70.37 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock "clk1" to destination pin "co" through register "cay" is 11.863 ns
    Info: + Longest clock path from clock "clk1" to source register is 5.257 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 1; CLK Node = 'clk1'
        Info: 2: + IC(0.611 ns) + CELL(0.183 ns) = 1.622 ns; Loc. = LC_X1_Y19_N2; Fanout = 9; COMB Node = 'clk~7'
        Info: 3: + IC(3.093 ns) + CELL(0.542 ns) = 5.257 ns; Loc. = LC_X35_Y29_N6; Fanout = 1; REG Node = 'cay'
        Info: Total cell delay = 1.553 ns ( 29.54 % )
        Info: Total interconnect delay = 3.704 ns ( 70.46 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 6.450 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y29_N6; Fanout = 1; REG Node = 'cay'
        Info: 2: + IC(2.514 ns) + CELL(0.366 ns) = 2.880 ns; Loc. = LC_X1_Y19_N4; Fanout = 1; COMB Node = 'co~12'
        Info: 3: + IC(1.194 ns) + CELL(2.376 ns) = 6.450 ns; Loc. = PIN_K21; Fanout = 0; PIN Node = 'co'
        Info: Total cell delay = 2.742 ns ( 42.51 % )
        Info: Total interconnect delay = 3.708 ns ( 57.49 % )
Info: Longest tpd from source pin "ss" to destination pin "co" is 7.933 ns
    Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L22; Fanout = 2; CLK Node = 'ss'
    Info: 2: + IC(3.455 ns) + CELL(0.183 ns) = 4.363 ns; Loc. = LC_X1_Y19_N4; Fanout = 1; COMB Node = 'co~12'
    Info: 3: + IC(1.194 ns) + CELL(2.376 ns) = 7.933 ns; Loc. = PIN_K21; Fanout = 0; PIN Node = 'co'
    Info: Total cell delay = 3.284 ns ( 41.40 % )
    Info: Total interconnect delay = 4.649 ns ( 58.60 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Oct 10 22:42:18 2007
    Info: Elapsed time: 00:00:01