📄 cdu60.tan.rpt
字号:
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[2] ; out1[1] ; clk2 ; clk2 ; None ; None ; 2.158 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out2[2] ; clk2 ; clk2 ; None ; None ; 2.113 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[2] ; out2[0] ; clk2 ; clk2 ; None ; None ; 2.108 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[1] ; out1[0] ; clk2 ; clk2 ; None ; None ; 2.075 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[1] ; out1[3] ; clk2 ; clk2 ; None ; None ; 2.075 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[1] ; out1[0] ; clk2 ; clk2 ; None ; None ; 2.061 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out2[1] ; clk2 ; clk2 ; None ; None ; 2.053 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[2] ; out1[3] ; clk2 ; clk2 ; None ; None ; 2.025 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; out1[2] ; clk2 ; clk2 ; None ; None ; 2.001 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; out1[1] ; clk2 ; clk2 ; None ; None ; 1.996 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[0] ; out1[3] ; clk2 ; clk2 ; None ; None ; 1.977 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; out2[0] ; clk2 ; clk2 ; None ; None ; 1.946 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out1[2] ; clk2 ; clk2 ; None ; None ; 1.944 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[0] ; out2[0] ; clk2 ; clk2 ; None ; None ; 1.943 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out1[1] ; clk2 ; clk2 ; None ; None ; 1.939 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[0] ; out1[3] ; clk2 ; clk2 ; None ; None ; 1.892 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out2[0] ; clk2 ; clk2 ; None ; None ; 1.889 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[2] ; out1[0] ; clk2 ; clk2 ; None ; None ; 1.869 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[0] ; out2[0] ; clk2 ; clk2 ; None ; None ; 1.858 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; out1[3] ; clk2 ; clk2 ; None ; None ; 1.858 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[0] ; out1[2] ; clk2 ; clk2 ; None ; None ; 1.839 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[0] ; out1[2] ; clk2 ; clk2 ; None ; None ; 1.754 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; out1[0] ; clk2 ; clk2 ; None ; None ; 1.707 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out1[3] ; clk2 ; clk2 ; None ; None ; 1.707 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; out1[0] ; clk2 ; clk2 ; None ; None ; 1.650 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[2] ; cay ; clk2 ; clk2 ; None ; None ; 1.464 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[1] ; cay ; clk2 ; clk2 ; None ; None ; 1.358 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[1] ; cay ; clk2 ; clk2 ; None ; None ; 1.332 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[0] ; out1[1] ; clk2 ; clk2 ; None ; None ; 1.317 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[0] ; out1[1] ; clk2 ; clk2 ; None ; None ; 1.232 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[2] ; cay ; clk2 ; clk2 ; None ; None ; 1.140 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[3] ; cay ; clk2 ; clk2 ; None ; None ; 1.020 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out2[3] ; cay ; clk2 ; clk2 ; None ; None ; 0.958 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; out1[0] ; out1[0] ; clk2 ; clk2 ; None ; None ; 0.846 ns ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------+------+------------+
; N/A ; None ; 11.863 ns ; cay ; co ; clk1 ;
; N/A ; None ; 11.827 ns ; cay ; co ; clk2 ;
; N/A ; None ; 11.639 ns ; cay ; co ; ss ;
; N/A ; None ; 10.843 ns ; out2[1] ; m[1] ; clk1 ;
; N/A ; None ; 10.807 ns ; out2[1] ; m[1] ; clk2 ;
; N/A ; None ; 10.644 ns ; out2[0] ; m[0] ; clk1 ;
; N/A ; None ; 10.619 ns ; out2[1] ; m[1] ; ss ;
; N/A ; None ; 10.608 ns ; out2[0] ; m[0] ; clk2 ;
; N/A ; None ; 10.420 ns ; out2[0] ; m[0] ; ss ;
; N/A ; None ; 9.695 ns ; out2[3] ; m[3] ; clk1 ;
; N/A ; None ; 9.659 ns ; out2[3] ; m[3] ; clk2 ;
; N/A ; None ; 9.471 ns ; out2[3] ; m[3] ; ss ;
; N/A ; None ; 9.027 ns ; out2[2] ; m[2] ; clk1 ;
; N/A ; None ; 8.991 ns ; out2[2] ; m[2] ; clk2 ;
; N/A ; None ; 8.803 ns ; out2[2] ; m[2] ; ss ;
+-------+--------------+------------+---------+------+------------+
+---------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 7.933 ns ; ss ; co ;
+-------+-------------------+-----------------+------+----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Wed Oct 10 22:42:18 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cdu60 -c cdu60 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "ss" is an undefined clock
Info: Assuming node "clk1" is an undefined clock
Info: Assuming node "clk2" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "clk~7" as buffer
Info: Clock "ss" has Internal fmax of 351.0 MHz between source register "out1[1]" and destination register "out2[3]" (period= 2.849 ns)
Info: + Longest register to register delay is 2.683 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y29_N9; Fanout = 4; REG Node = 'out1[1]'
Info: 2: + IC(0.393 ns) + CELL(0.280 ns) = 0.673 ns; Loc. = LC_X35_Y29_N5; Fanout = 3; COMB Node = 'process0~51'
Info: 3: + IC(0.344 ns) + CELL(0.183 ns) = 1.200 ns; Loc. = LC_X35_Y29_N8; Fanout = 6; COMB Node = 'process0~1'
Info: 4: + IC(0.525 ns) + CELL(0.341 ns) = 2.066 ns; Loc. = LC_X35_Y29_N1; Fanout = 2; COMB Node = 'out2[0]~45COUT1_50'
Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 2.126 ns; Loc. = LC_X35_Y29_N2; Fanout = 2; COMB Node = 'out2[1]~46COUT1'
Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 2.186 ns; Loc. = LC_X35_Y29_N3; Fanout = 1; COMB Node = 'out2[2]~47COUT1_51'
Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.683 ns; Loc. = LC_X35_Y29_N4; Fanout = 5; REG Node = 'out2[3]'
Info: Total cell delay = 1.421 ns ( 52.96 % )
Info: Total interconnect delay = 1.262 ns ( 47.04 % )
Info: - Smallest clock skew is 0.000 ns
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