cdu60.map.summary

来自「一些很好的FPGA设计实例」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Wed Oct 10 22:41:56 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : cdu60
Top-level Entity Name : cdu60
Family : Stratix
Total logic elements : 18
Total pins : 12
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0