cdu60.vhd

一些很好的FPGA设计实例

--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--******************************************************

ENTITY cdu60 IS-- 分钟显示模块
	PORT(
          	clk1,clk2,ss: in std_logic;
   --clk1输入1/60HZ时钟,clk2调分递增频率 ss调分信号
            co: out std_logic;--进位输出
            m:  out std_logic_vector(7 downto 0)--显示输出			        
		);
END cdu60;

--*******************************************************

ARCHITECTURE aa OF cdu60 IS
	SIGNAL out1,out2 : integer range 0 to 9;
	SIGNAL out3,out4 : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
	SIGNAL clk ,cay: STD_LOGIC;
BEGIN
    co <= cay when ss ='0' else '0';--调分时禁止进位信号输出
    cLK <= clk1 when ss ='0' else clk2;--调分时切换驱动频率到2HZ
process(clk)
    begin
    if clk'event and clk ='1' then
       if (out2<=5)and(out1<=9)then --摸59计数
       out1<=0;
       out2<=0;
       cay<='1';  
       else      
       out1 <=  out1 +1;
       cay<='0';
          if out1 =9 and out2 /=5 then 
             out1<=0;
             out2 <=  out2 +1;
             cay<='0'; 
         end if;
       end if;
    end if;

out3 <= conv_std_logic_vector(out1,4);--进制转换
out3 <= conv_std_logic_vector(out2,4);
m <= out4& out3;
end process;
end aa;