control.tan.rpt

一些很好的FPGA设计实例

+---------------------------------------------------------------+
; tsu                                                           ;
+-------+--------------+------------+-------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To     ; To Clock ;
+-------+--------------+------------+-------+--------+----------+
; N/A   ; None         ; 1.524 ns   ; start ; sstart ; clk      ;
+-------+--------------+------------+-------+--------+----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+----------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To        ; From Clock ;
+-------+--------------+------------+----------+-----------+------------+
; N/A   ; None         ; 7.410 ns   ; asstart  ; startstop ; clk        ;
; N/A   ; None         ; 6.422 ns   ; count[3] ; clks      ; clk        ;
+-------+--------------+------------+----------+-----------+------------+


+---------------------------------------------------------------------+
; th                                                                  ;
+---------------+-------------+-----------+-------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To     ; To Clock ;
+---------------+-------------+-----------+-------+--------+----------+
; N/A           ; None        ; -1.414 ns ; start ; sstart ; clk      ;
+---------------+-------------+-----------+-------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Oct 10 23:32:00 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off control -c control --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "sstart" as buffer
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "count[1]" and destination register "count[3]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.980 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y27_N7; Fanout = 3; REG Node = 'count[1]'
            Info: 2: + IC(0.522 ns) + CELL(0.458 ns) = 0.980 ns; Loc. = LC_X1_Y27_N9; Fanout = 3; REG Node = 'count[3]'
            Info: Total cell delay = 0.458 ns ( 46.73 % )
            Info: Total interconnect delay = 0.522 ns ( 53.27 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.928 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.558 ns) + CELL(0.542 ns) = 2.928 ns; Loc. = LC_X1_Y27_N9; Fanout = 3; REG Node = 'count[3]'
                Info: Total cell delay = 1.370 ns ( 46.79 % )
                Info: Total interconnect delay = 1.558 ns ( 53.21 % )
            Info: - Longest clock path from clock "clk" to source register is 2.928 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.558 ns) + CELL(0.542 ns) = 2.928 ns; Loc. = LC_X1_Y27_N7; Fanout = 3; REG Node = 'count[1]'
                Info: Total cell delay = 1.370 ns ( 46.79 % )
                Info: Total interconnect delay = 1.558 ns ( 53.21 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "sstart" (data pin = "start", clock pin = "clk") is 1.524 ns
    Info: + Longest pin to register delay is 4.496 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_V4; Fanout = 1; PIN Node = 'start'
        Info: 2: + IC(3.177 ns) + CELL(0.085 ns) = 4.496 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; REG Node = 'sstart'
        Info: Total cell delay = 1.319 ns ( 29.34 % )
        Info: Total interconnect delay = 3.177 ns ( 70.66 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.982 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; REG Node = 'sstart'
        Info: Total cell delay = 1.370 ns ( 45.94 % )
        Info: Total interconnect delay = 1.612 ns ( 54.06 % )
Info: tco from clock "clk" to destination pin "startstop" through register "asstart" is 7.410 ns
    Info: + Longest clock path from clock "clk" to source register is 4.082 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.612 ns) + CELL(0.698 ns) = 3.138 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; REG Node = 'sstart'
        Info: 3: + IC(0.402 ns) + CELL(0.542 ns) = 4.082 ns; Loc. = LC_X52_Y1_N4; Fanout = 2; REG Node = 'asstart'
        Info: Total cell delay = 2.068 ns ( 50.66 % )
        Info: Total interconnect delay = 2.014 ns ( 49.34 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.172 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y1_N4; Fanout = 2; REG Node = 'asstart'
        Info: 2: + IC(0.796 ns) + CELL(2.376 ns) = 3.172 ns; Loc. = PIN_V3; Fanout = 0; PIN Node = 'startstop'
        Info: Total cell delay = 2.376 ns ( 74.91 % )
        Info: Total interconnect delay = 0.796 ns ( 25.09 % )
Info: th for register "sstart" (data pin = "start", clock pin = "clk") is -1.414 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.982 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; REG Node = 'sstart'
        Info: Total cell delay = 1.370 ns ( 45.94 % )
        Info: Total interconnect delay = 1.612 ns ( 54.06 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.496 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_V4; Fanout = 1; PIN Node = 'start'
        Info: 2: + IC(3.177 ns) + CELL(0.085 ns) = 4.496 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; REG Node = 'sstart'
        Info: Total cell delay = 1.319 ns ( 29.34 % )
        Info: Total interconnect delay = 3.177 ns ( 70.66 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Oct 10 23:32:00 2007
    Info: Elapsed time: 00:00:01