control.fit.summary

一些很好的FPGA设计实例

Fitter Status : Successful - Wed Oct 10 23:31:50 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : control
Top-level Entity Name : control
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 6 / 10,570 ( < 1 % )
Total pins : 4 / 336 ( 1 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )