control.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "ITDB_TSU_RESULT" "sstart start clk 1.524 ns register " "Info: tsu for register \"sstart\" (data pin = \"start\", clock pin = \"clk\") is 1.524 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.496 ns + Longest pin register " "Info: + Longest pin to register delay is 4.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns start 1 PIN PIN_V4 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_V4; Fanout = 1; PIN Node = 'start'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.177 ns) + CELL(0.085 ns) 4.496 ns sstart 2 REG LC_X52_Y1_N2 1 " "Info: 2: + IC(3.177 ns) + CELL(0.085 ns) = 4.496 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; REG Node = 'sstart'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.262 ns" { start sstart } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 29.34 % ) " "Info: Total cell delay = 1.319 ns ( 29.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.177 ns ( 70.66 % ) " "Info: Total interconnect delay = 3.177 ns ( 70.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.496 ns" { start sstart } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.496 ns" { start start~out0 sstart } { 0.000ns 0.000ns 3.177ns } { 0.000ns 1.234ns 0.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.982 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.982 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.542 ns) 2.982 ns sstart 2 REG LC_X52_Y1_N2 1 " "Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; REG Node = 'sstart'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.154 ns" { clk sstart } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.94 % ) " "Info: Total cell delay = 1.370 ns ( 45.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.612 ns ( 54.06 % ) " "Info: Total interconnect delay = 1.612 ns ( 54.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.982 ns" { clk sstart } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.982 ns" { clk clk~out0 sstart } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.496 ns" { start sstart } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.496 ns" { start start~out0 sstart } { 0.000ns 0.000ns 3.177ns } { 0.000ns 1.234ns 0.085ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.982 ns" { clk sstart } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.982 ns" { clk clk~out0 sstart } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk startstop asstart 7.410 ns register " "Info: tco from clock \"clk\" to destination pin \"startstop\" through register \"asstart\" is 7.410 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.082 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 4.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.698 ns) 3.138 ns sstart 2 REG LC_X52_Y1_N2 1 " "Info: 2: + IC(1.612 ns) + CELL(0.698 ns) = 3.138 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; REG Node = 'sstart'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.310 ns" { clk sstart } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.402 ns) + CELL(0.542 ns) 4.082 ns asstart 3 REG LC_X52_Y1_N4 2 " "Info: 3: + IC(0.402 ns) + CELL(0.542 ns) = 4.082 ns; Loc. = LC_X52_Y1_N4; Fanout = 2; REG Node = 'asstart'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.944 ns" { sstart asstart } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns ( 50.66 % ) " "Info: Total cell delay = 2.068 ns ( 50.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.014 ns ( 49.34 % ) " "Info: Total interconnect delay = 2.014 ns ( 49.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.082 ns" { clk sstart asstart } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.082 ns" { clk clk~out0 sstart asstart } { 0.000ns 0.000ns 1.612ns 0.402ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.172 ns + Longest register pin " "Info: + Longest register to pin delay is 3.172 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns asstart 1 REG LC_X52_Y1_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y1_N4; Fanout = 2; REG Node = 'asstart'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { asstart } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.796 ns) + CELL(2.376 ns) 3.172 ns startstop 2 PIN PIN_V3 0 " "Info: 2: + IC(0.796 ns) + CELL(2.376 ns) = 3.172 ns; Loc. = PIN_V3; Fanout = 0; PIN Node = 'startstop'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.172 ns" { asstart startstop } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns ( 74.91 % ) " "Info: Total cell delay = 2.376 ns ( 74.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.796 ns ( 25.09 % ) " "Info: Total interconnect delay = 0.796 ns ( 25.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.172 ns" { asstart startstop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.172 ns" { asstart startstop } { 0.000ns 0.796ns } { 0.000ns 2.376ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.082 ns" { clk sstart asstart } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.082 ns" { clk clk~out0 sstart asstart } { 0.000ns 0.000ns 1.612ns 0.402ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.172 ns" { asstart startstop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.172 ns" { asstart startstop } { 0.000ns 0.796ns } { 0.000ns 2.376ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "sstart start clk -1.414 ns register " "Info: th for register \"sstart\" (data pin = \"start\", clock pin = \"clk\") is -1.414 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.982 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.982 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.542 ns) 2.982 ns sstart 2 REG LC_X52_Y1_N2 1 " "Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; REG Node = 'sstart'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.154 ns" { clk sstart } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.94 % ) " "Info: Total cell delay = 1.370 ns ( 45.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.612 ns ( 54.06 % ) " "Info: Total interconnect delay = 1.612 ns ( 54.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.982 ns" { clk sstart } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.982 ns" { clk clk~out0 sstart } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.496 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns start 1 PIN PIN_V4 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_V4; Fanout = 1; PIN Node = 'start'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.177 ns) + CELL(0.085 ns) 4.496 ns sstart 2 REG LC_X52_Y1_N2 1 " "Info: 2: + IC(3.177 ns) + CELL(0.085 ns) = 4.496 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; REG Node = 'sstart'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.262 ns" { start sstart } "NODE_NAME" } } { "control.vhd" "" { Text "E:/数字秒表的设计/control/control.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 29.34 % ) " "Info: Total cell delay = 1.319 ns ( 29.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.177 ns ( 70.66 % ) " "Info: Total interconnect delay = 3.177 ns ( 70.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.496 ns" { start sstart } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.496 ns" { start start~out0 sstart } { 0.000ns 0.000ns 3.177ns } { 0.000ns 1.234ns 0.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.982 ns" { clk sstart } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.982 ns" { clk clk~out0 sstart } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.496 ns" { start sstart } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.496 ns" { start start~out0 sstart } { 0.000ns 0.000ns 3.177ns } { 0.000ns 1.234ns 0.085ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 10 23:32:00 2007 " "Info: Processing ended: Wed Oct 10 23:32:00 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}