control.sim.vwf

一些很好的FPGA设计实例

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 1000000000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("clks")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("start")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("startstop")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 100000;
			LEVEL 0 FOR 5000.0;
			LEVEL 1 FOR 5000.0;
		}
	}
}

TRANSITION_LIST("clks")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 75006.422;
		NODE
		{
			REPEAT = 9999;
			LEVEL 1 FOR 20000.0;
			LEVEL 0 FOR 80000.0;
		}
		LEVEL 1 FOR 20000.0;
		LEVEL 0 FOR 4993.578;
	}
}

TRANSITION_LIST("start")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 87040.0;
		LEVEL 1 FOR 30720.0;
		LEVEL 0 FOR 61440.0;
		LEVEL 1 FOR 25600.0;
		LEVEL 0 FOR 61440.0;
		LEVEL 1 FOR 35840.0;
		LEVEL 0 FOR 999697920.0;
	}
}

TRANSITION_LIST("startstop")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 95007.41;
		LEVEL 1 FOR 90000.0;
		LEVEL 0 FOR 90000.0;
		LEVEL 1 FOR 999724992.59;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clks";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "start";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "startstop";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 11325;
	MASTER = TRUE;
}
;