control.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 41 行

--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--******************************************************

ENTITY control IS
	PORT(
          	clk,start: in std_logic; 
           startstop,clks : out std_logic
		);
END control;

--*******************************************************

ARCHITECTURE aa OF control IS
	SIGNAL sstart,asstart : STD_LOGIC;
	SIGNAL  count  : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGIN
clk_label:process(clk)
    begin
    if clk'event and clk ='1' then
       if count = "1001" then count <="0000";
       else count <= count +1;
       end if;
       sstart <= start;
    end if;
end process clk_label;

clkss_label:process(sstart)
    begin
    if sstart'event and sstart ='1' then--每按一次使能信号状态变化一次
    asstart <= not asstart;
    end if;
end process clkss_label; 
startstop <=asstart;
clks <= count(3);--达到10分频的效果
end aa;