gollstt.tan.qmsg

实现FPGA的加密程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register pres_s.state_bit_1 register pres_s.state_bit_1 227.27 MHz 4.4 ns Internal " "Info: Clock \"clk\" has Internal fmax of 227.27 MHz between source register \"pres_s.state_bit_1\" and destination register \"pres_s.state_bit_1\" (period= 4.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.400 ns + Longest register register " "Info: + Longest register to register delay is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pres_s.state_bit_1 1 REG LC3 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pres_s.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.500 ns) 2.400 ns pres_s.state_bit_1 2 REG LC3 6 " "Info: 2: + IC(0.900 ns) + CELL(1.500 ns) = 2.400 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { pres_s.state_bit_1 pres_s.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 62.50 % ) " "Info: Total cell delay = 1.500 ns ( 62.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 37.50 % ) " "Info: Total interconnect delay = 0.900 ns ( 37.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { pres_s.state_bit_1 pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { pres_s.state_bit_1 {} pres_s.state_bit_1 {} } { 0.000ns 0.900ns } { 0.000ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns clk 1 CLK PIN_37 2 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns pres_s.state_bit_1 2 REG LC3 6 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns clk 1 CLK PIN_37 2 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns pres_s.state_bit_1 2 REG LC3 6 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { pres_s.state_bit_1 pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { pres_s.state_bit_1 {} pres_s.state_bit_1 {} } { 0.000ns 0.900ns } { 0.000ns 1.500ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "ITDB_TSU_RESULT" "pres_s.state_bit_1 done2 clk 2.900 ns register " "Info: tsu for register \"pres_s.state_bit_1\" (data pin = \"done2\", clock pin = \"clk\") is 2.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.100 ns + Longest pin register " "Info: + Longest pin to register delay is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns done2 1 PIN PIN_15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_15; Fanout = 3; PIN Node = 'done2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { done2 } "NODE_NAME" } } { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.500 ns) 3.100 ns pres_s.state_bit_1 2 REG LC3 6 " "Info: 2: + IC(0.900 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { done2 pres_s.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 70.97 % ) " "Info: Total cell delay = 2.200 ns ( 70.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 29.03 % ) " "Info: Total interconnect delay = 0.900 ns ( 29.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { done2 pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { done2 {} done2~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns clk 1 CLK PIN_37 2 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns pres_s.state_bit_1 2 REG LC3 6 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { done2 pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { done2 {} done2~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 1.500ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk cmp_ena pres_s.state_bit_1 6.000 ns register " "Info: tco from clock \"clk\" to destination pin \"cmp_ena\" through register \"pres_s.state_bit_1\" is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns clk 1 CLK PIN_37 2 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns pres_s.state_bit_1 2 REG LC3 6 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest register pin " "Info: + Longest register to pin delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pres_s.state_bit_1 1 REG LC3 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pres_s.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(2.100 ns) 3.000 ns pres_s.st3~20 2 COMB LC2 1 " "Info: 2: + IC(0.900 ns) + CELL(2.100 ns) = 3.000 ns; Loc. = LC2; Fanout = 1; COMB Node = 'pres_s.st3~20'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { pres_s.state_bit_1 pres_s.st3~20 } "NODE_NAME" } } { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.800 ns cmp_ena 3 PIN PIN_43 0 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 3.800 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'cmp_ena'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { pres_s.st3~20 cmp_ena } "NODE_NAME" } } { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 76.32 % ) " "Info: Total cell delay = 2.900 ns ( 76.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 23.68 % ) " "Info: Total interconnect delay = 0.900 ns ( 23.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { pres_s.state_bit_1 pres_s.st3~20 cmp_ena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.800 ns" { pres_s.state_bit_1 {} pres_s.st3~20 {} cmp_ena {} } { 0.000ns 0.900ns 0.000ns } { 0.000ns 2.100ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { pres_s.state_bit_1 pres_s.st3~20 cmp_ena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.800 ns" { pres_s.state_bit_1 {} pres_s.st3~20 {} cmp_ena {} } { 0.000ns 0.900ns 0.000ns } { 0.000ns 2.100ns 0.800ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "ITDB_TH_RESULT" "pres_s.state_bit_1 done2 clk -1.000 ns register " "Info: th for register \"pres_s.state_bit_1\" (data pin = \"done2\", clock pin = \"clk\") is -1.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns clk 1 CLK PIN_37 2 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns pres_s.state_bit_1 2 REG LC3 6 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.600 ns + " "Info: + Micro hold delay of destination is 0.600 ns" {  } {  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns done2 1 PIN PIN_15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_15; Fanout = 3; PIN Node = 'done2'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { done2 } "NODE_NAME" } } { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.500 ns) 3.100 ns pres_s.state_bit_1 2 REG LC3 6 " "Info: 2: + IC(0.900 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC3; Fanout = 6; REG Node = 'pres_s.state_bit_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { done2 pres_s.state_bit_1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 70.97 % ) " "Info: Total cell delay = 2.200 ns ( 70.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 29.03 % ) " "Info: Total interconnect delay = 0.900 ns ( 29.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { done2 pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { done2 {} done2~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { clk pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { clk {} clk~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { done2 pres_s.state_bit_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { done2 {} done2~out {} pres_s.state_bit_1 {} } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 1.500ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "Classic Timing Analyzer" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 14 22:23:16 2008 " "Info: Processing ended: Thu Aug 14 22:23:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Classic Timing Analyzer" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Classic Timing Analyzer" 0}